JPH043663B2 - - Google Patents
Info
- Publication number
- JPH043663B2 JPH043663B2 JP18383381A JP18383381A JPH043663B2 JP H043663 B2 JPH043663 B2 JP H043663B2 JP 18383381 A JP18383381 A JP 18383381A JP 18383381 A JP18383381 A JP 18383381A JP H043663 B2 JPH043663 B2 JP H043663B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- grain size
- diffusion
- pocl
- crystal grain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 8
- 239000012808 vapor phase Substances 0.000 claims 1
- 239000013078 crystal Substances 0.000 description 12
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000010410 layer Substances 0.000 description 8
- 239000007789 gas Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Silicon Compounds (AREA)
Description
【発明の詳細な説明】
本発明は多結晶シリコン層に均一にリン(P)
などの不純物を添加する方法に関するものであ
る。一般に多結晶シリコンの形成はモノシラン
(SiH4)ガスをソースガスとして、常圧か減圧気
相成長法により行われる。従来この多結晶シリコ
ン層に不純物をドービングする際、多結晶Si層の
結晶粒径について考慮が払われていなかつたが、
今回多結晶シリコン層にPを、例えばPOCl3をソ
ースとして拡散添加する場合に結晶粒径により添
加濃度が変化する事が判明した。本発明はこの点
を考慮し、結晶粒径は100nm以下にする条件で多
結晶シリコン層を形成するならば、POCl3拡散の
温度が1000℃以下の比較的低温であつてもウエー
ハ面内、且つウエーハ間の添加濃度を均一に保ち
得る方法を提供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for uniformly adding phosphorus (P) to a polycrystalline silicon layer.
It relates to a method of adding impurities such as. Generally, polycrystalline silicon is formed by normal pressure or reduced pressure vapor phase growth using monosilane (SiH 4 ) gas as a source gas. Conventionally, when doping this polycrystalline silicon layer with impurities, no consideration was given to the crystal grain size of the polycrystalline silicon layer.
This time, it has been found that when P is diffused and added to a polycrystalline silicon layer using, for example, POCl 3 as a source, the doping concentration changes depending on the crystal grain size. The present invention takes this point into consideration, and if a polycrystalline silicon layer is formed under the condition that the crystal grain size is 100 nm or less, even if the POCl 3 diffusion temperature is relatively low, 1000°C or less, within the wafer surface. Moreover, it provides a method that can maintain a uniform doping concentration between wafers.
実施例
多結晶シリコン層を低圧気相成長法により、
1000Å厚の二酸化シリコン(SiO2)上に3500Å
形成する。ソースガスはSiH4で窒素(N2)ガス
をベースとし、圧力は1.0Torr、形成温度は500
〜850℃の範囲で行つた。このようにして形成し
た多結晶シリコン層にPをPOCl3をソースとして
拡散した。拡散温度と時間は1000℃、25分と、
875℃、20分の二通り実施した。Example: A polycrystalline silicon layer is grown by low pressure vapor phase epitaxy.
3500Å on 1000Å thick silicon dioxide (SiO 2 )
Form. The source gas is SiH4 based on nitrogen ( N2 ) gas, the pressure is 1.0Torr, and the formation temperature is 500℃.
The temperature range was ~850°C. P was diffused into the polycrystalline silicon layer thus formed using POCl 3 as a source. The diffusion temperature and time were 1000℃ and 25 minutes.
Two tests were conducted at 875°C for 20 minutes.
第1図に示すように、1000℃のPOCl3拡散の場
合には、拡散後の表面層抵抗ρsの値はほぼ20Ω/
□であり、ウエーハ面内、ならびにウエーハ間の
ρsの不均一性は±2%以内に保つことができる。 As shown in Figure 1, in the case of POCl 3 diffusion at 1000℃, the value of the surface layer resistance ρ s after diffusion is approximately 20Ω/
□, and the nonuniformity of ρ s within the wafer surface and between wafers can be maintained within ±2%.
しかし、低温の875℃でPOCl3拡散を行つた場
合には第1図に示すように、ρsの不均一性は大き
く、その程度は多結晶シリコンの形成温度に大き
く依存する。不均一性を±2%以内に抑えるため
には形成温度は600℃以下あるいは700℃以上を選
ばねばならないことが理解できる。 However, when POCl 3 diffusion is performed at a low temperature of 875° C., as shown in FIG. 1, the non-uniformity of ρ s is large, and the degree of non-uniformity greatly depends on the formation temperature of polycrystalline silicon. It can be seen that in order to suppress the non-uniformity within ±2%, the formation temperature must be selected to be 600° C. or lower or 700° C. or higher.
この原因を究明するために以下に示す実験を行
つた。まず低圧気相成長後の多結晶シリコン層の
結晶粒径ならびに多結晶シリコンにPOCl3拡散を
実施した試料の結晶粒径を、透過電子顕微鏡によ
り観察した。この結晶を第2図、第3図に示す
が、多結晶形成直後には第2図に示す様に、結晶
粒径は形成温度に依存する。一方POCl3拡散を施
した試料の結晶粒径は、1000℃の場合には良く識
られているように不純物Pの高濃度添加による粒
径の増大が観察されるが、多結晶形成温度には依
存せずほぼ5000Åを維持しているのに対して、
POCl3拡散875℃の場合には多結晶形成温度に大
きく依存する。875℃拡散ではもともとの結晶粒
径が大きい場合には粒径の成長が抑止され、拡散
後のρs値も70Ω/□と高くなつてしまう。 In order to investigate the cause of this, the following experiment was conducted. First, the crystal grain size of the polycrystalline silicon layer after low-pressure vapor phase growth and the crystal grain size of the sample in which POCl 3 was diffused into polycrystalline silicon were observed using a transmission electron microscope. This crystal is shown in FIGS. 2 and 3. Immediately after polycrystal formation, as shown in FIG. 2, the crystal grain size depends on the formation temperature. On the other hand, the crystal grain size of the sample subjected to POCl 3 diffusion is observed to increase at 1000°C due to the addition of a high concentration of impurity P, but at While it maintains almost 5000Å without depending on
In the case of POCl 3 diffusion at 875°C, it is highly dependent on the polycrystal formation temperature. In 875°C diffusion, if the original crystal grain size is large, the growth of the grain size is inhibited, and the ρ s value after diffusion becomes as high as 70Ω/□.
第1図と、第2,3図とを合わせ考えるなら
ば、ρsの不均一性は多結晶形成直後の結晶粒径に
大きく依存していることが理解される。 If we consider FIG. 1 and FIGS. 2 and 3 together, it will be understood that the non-uniformity of ρ s is largely dependent on the crystal grain size immediately after polycrystal formation.
近年の半導体素子の微細化に伴ないPOCl3拡散
の温度も低温化される傾向に有り、この場合特に
この結晶粒径に注意を払う事が重要となる。 With the miniaturization of semiconductor devices in recent years, the temperature of POCl 3 diffusion tends to be lowered, and in this case, it is important to pay particular attention to the crystal grain size.
したがつて、第1図乃至第3図から明らかなよ
うに、多結晶シリコンの形成温度をほぼ500〜600
℃もしくは700〜850℃とすれば、多結晶シリコン
形成後の結晶粒径は小さく、また、POCl3拡散後
の粒径の増大も認められ、低温度で拡散を行つて
も、ρsの変動は極めて小さい。 Therefore, as is clear from FIGS. 1 to 3, the temperature for forming polycrystalline silicon is approximately 500 to 600.
℃ or 700 to 850℃, the crystal grain size after polycrystalline silicon formation is small, and an increase in the grain size after POCl 3 diffusion is also observed . is extremely small.
したがつて、ほぼ500〜600℃もしくは700〜850
℃で多結晶シリコンを形成し、不純物拡散温度を
低くすれば、高集積密度を有する半導体装置の形
成に極めて有効である。 Therefore, approximately 500-600℃ or 700-850℃
Forming polycrystalline silicon at a temperature of .degree. C. and lowering the impurity diffusion temperature is extremely effective in forming semiconductor devices with high integration density.
なお、上記説明は便宜上、リンを拡散した場合
について行つたが、リンのみではなく、BやAs
などの各種不純物を拡散する場合も同じ結果が得
られ、これらの不純物を拡散する場合にも適用す
ることができる。 For convenience, the above explanation is based on the case where phosphorus is diffused, but not only phosphorus but also B and A s
The same results can be obtained when diffusing various impurities such as, and the method can also be applied to diffusing these impurities.
第1図乃至第3図は本発明の原理を説明するた
めの曲線図である。
1 to 3 are curve diagrams for explaining the principle of the present invention.
Claims (1)
応によつて多結晶シリコン膜を形成する工程と、
上記多結晶シリコン膜内に不純物を拡散する工程
を含むことを特徴とする不純物拡散方法。1. A step of forming a polycrystalline silicon film by vapor phase reaction on a wafer kept at 500 to 550°C;
An impurity diffusion method comprising the step of diffusing an impurity into the polycrystalline silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18383381A JPS5888114A (en) | 1981-11-18 | 1981-11-18 | Process for impurity diffusion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18383381A JPS5888114A (en) | 1981-11-18 | 1981-11-18 | Process for impurity diffusion |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5888114A JPS5888114A (en) | 1983-05-26 |
| JPH043663B2 true JPH043663B2 (en) | 1992-01-23 |
Family
ID=16142634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18383381A Granted JPS5888114A (en) | 1981-11-18 | 1981-11-18 | Process for impurity diffusion |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5888114A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06101535B2 (en) * | 1984-04-17 | 1994-12-12 | 株式会社東芝 | Method for forming semiconductor resistance layer |
-
1981
- 1981-11-18 JP JP18383381A patent/JPS5888114A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5888114A (en) | 1983-05-26 |
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