JPH0831408B2 - Semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a semiconductor device (device) using an epitaxial wafer using a P ⁺ substrate containing a high concentration of boron.

[Conventional technology]

Conventionally, an epitaxial wafer formed by forming an epitaxial film on this type of P ⁺ substrate is used for highly integrated memory circuit elements, ultra-high speed memory circuit elements, etc. for the purpose of preventing latch-up between elements and α-ray soft error. Is used for. At this time, it is effective for the P ⁺ substrate to contain boron as high concentration as possible and to have low resistance in order to prevent latch-up and prevent α-ray soft error. Further, since the silicon epitaxial film formed on the P ⁺ substrate serves as a device formation region, an epitaxial film having a resistivity that is two orders of magnitude higher than that of the P ⁺ substrate is practically used. However, the lattice constant of the P ⁺ substrate containing boron decreases as the boron concentration increases, and when the resistance is lowered, the difference in lattice constant from the epitaxial film becomes large and misfit dislocations occur. Therefore, the conventional semiconductor device using this type of epitaxial wafer uses an epitaxial wafer in which the content of boron concentration is suppressed in order to prevent the occurrence of this misfit dislocation.

[Problems to be Solved by the Invention]

Since the semiconductor device using the conventional silicon epitaxial wafer as described above is suppressed to the extent that misfit dislocations boron content of P ⁺ substrate does not occur, can not sufficiently reduce the resistance of the P ⁺ substrate, latchup, alpha There is a drawback that sufficient measures cannot be taken to improve device characteristics, such as measures to prevent line soft errors.

Further, since the P ⁺ substrate has a property that oxygen precipitation is likely to occur when the boron concentration is in a low concentration range where the occurrence of misfit dislocations is suppressed, these P ⁺ substrates have an excessive oxygen precipitation defect. There is a defect that causes device failure.

[Means for solving the problem]

The semiconductor device of the present invention is formed using a silicon epitaxial wafer consisting of an epitaxial film having two or more orders of magnitude higher resistivity than P ⁺ substrate and the P ⁺ substrate containing boron at a high concentration, and P ⁺ substrate and the epitaxial It has misfit dislocations based on the difference in the lattice constants of the film.

The present inventor is aware that the misfit dislocations that occur in a silicon epitaxial wafer using such a P ⁺ substrate are the dislocations that are formed on the P ⁺ substrate side near the interface between the epitaxial film and the P ⁺ substrate and that occur at the LOCOS edge or the like. It has been found that the properties are largely different, and the device formed on the epitaxial film is not adversely affected without protruding to the silicon epitaxial film side even after the subsequent heat treatment process. On the contrary, it has been found that this misfit dislocation has a strong gettering effect for trapping contamination such as heavy metal elements mixed in in the device manufacturing process.

Since the semiconductor device including the misfit dislocation of the present invention is invented by the above-mentioned discoveries made by the present inventor, the idea that the conventional misfit dislocation adversely affects the device is basically turned over, It aims to lower the resistance of the P ⁺ substrate by positively incorporating misfit dislocations.

In short, according to the present invention, in the silicon epitaxial wafer, by significantly increasing the boron content of the P ⁺ substrate, the electrical resistivity thereof can be significantly reduced as compared with the conventional one.

〔Example〕

The present invention will be described by way of specific examples. FIG. 1 is a sectional view for explaining an embodiment of the present invention. A silicon epitaxial film 3 having a film thickness of 15 μm was formed on a 6-inch (100) P ⁺ substrate 1 having an electric resistivity of 0.007 Ω · cm to which boron was added at a high concentration. In the epitaxial growth, the growth temperature was 1150 ° C., and the growth gas was silicon tetrachloride (SiCl ₄ and hydrogen (H ₂ ), B ₂ H ₆ (diborane). The electrical resistivity of the silicon epitaxial film 3 was B ₂ H _{2. 6} amount was adjusted to a 10 [Omega · cm. the silicon epitaxial wafer was subjected to epitaxial growth in the reference sample P ⁺ substrate normal electrical resistivity 0.015 · cm silicon epitaxial wafer under the same conditions (hereinafter A normal epitaxial wafer) was prepared.

Using both silicon epitaxial wafers above, 1
A megabit dynamic random access memory device (hereinafter referred to as 1MDRAM device) was prepared, and the yield and accumulated charge retention time of the device were compared. 1M DRAM according to this embodiment
The device yield was improved by 30% compared to a 1MDRAM device using a normal silicon epitaxial wafer (hereinafter referred to as a normal 1MDRAM device). Further, the 1MDRAM device according to the present example also increased the accumulated charge retention time by 3.5 times as compared with the 1MDRAM device using a normal epitaxial wafer. This is considered to be due to the lower resistance of the P ⁺ substrate, the improvement of latch-up, the α-ray soft error resistance, and the gettering ability.

Further, copper was diffused as a heavy metal into the silicon epitaxial wafer used for the 1M DRAM element of the above-described Example, and the depth of misfit dislocation generation was evaluated by observing a cross section with a transmission electron microscope. Also, by secondary ion mass spectrometry,
The gettering position of copper was evaluated. As shown in Fig. 2, misfit dislocations are generated only in the vicinity of the P / P ⁺ interface, and copper is concentrated at the misfit dislocation generation sites, and in the epitaxial silicon film that becomes the active region of the device. The amount was below the lower limit of detection.

From this result, misfit dislocations are generated only in the vicinity of the P / P ⁺ interface and are not generated in the epitaxial silicon film 3 which becomes the active region 4 of the device, so that they are formed on the epitaxial film 3 by the misfit dislocations. It does not adversely affect the device, and on the contrary, misfit dislocations have a strong gettering effect that captures contamination such as heavy metal elements such as copper that are mixed in during the device manufacturing process. There is.

Next, an example of experimentally obtaining the misfit dislocation generation limit will be described. Electrical resistivity of high concentration of boron 0.
A 4 inch (100) P ⁺ substrate of 003, 0.008, 0.015, 0.032 Ω · cm was prepared, and an epitaxial silicon film was formed on this P ⁺ substrate in various film thicknesses. In the epitaxial growth, 1100 ° C. was used as the growth temperature, and dichlorosilane (SiH ₂ Cl ₂ ) and hydrogen (H ₂ ) and B ₂ H ₂ (diborane) were used as the growth gas. Thickness of epitaxial silicon film is 1 to 70μ
m was used. At that time, the electrical resistivity of the P ⁺ substrate is 0.01Ω ・ cm
In the following cases, the thickness is changed by 1 μm and the value is 0.01Ω.
・ When the thickness was more than cm, the thickness was changed by 2 μm and the growth was performed. The electric resistivity of the epitaxial silicon film was set to 10 Ω · cm by adjusting the amount of B ₂ H ₆ .

Next, the presence or absence of misfit dislocations was determined by observing the silicon epitaxial wafer having undergone such epitaxial growth by an X-ray topography. FIG. 3 shows the relationship between the electrical resistivity ρ of the P ⁺ substrate obtained by such a method and the critical epitaxial silicon film thickness hc at which misfit dislocations occur. In the shaded area in FIG. 3, the occurrence of misfit dislocations was not seen. Next, based on this experimental data, we derived the relationship between the critical epitaxial film thickness hc at which misfit dislocations occur and the electrical resistivity ρ of the P ⁺ substrate. In the present invention, hc = 0.
57 ρ ^1.38 (1 ≦ ρ ≦ 30, ρ: 10 ⁻³ Ω · cm unit, hc: μm unit).

Next, an example in which the present invention is applied to a bipolar device will be described. Electrical resistivity with high concentration of boron 0.00
A 10 μm thick silicon epitaxial film was formed on a 4-inch (100) P ⁺ substrate of 5 Ω · cm. Boron diffuses from the P ⁺ substrate into the epitaxial film during the growth of the epitaxial film and subsequent heat treatment, and the electrical resistivity of the region of the epitaxial film near the P ⁺ substrate interface changes. The epitaxial film thickness is required to be 10 μm or more in order to avoid the influence and to manufacture semiconductor devices with high yield. In the epitaxial growth, 1100 ° C. was used as the growth temperature, and dichlorosilane (SiH ₂ Cl ₂ ) and hydrogen (H ₂ ) and B ₂ H ₆ (diborane) were used as the growth gas. The electrical resistivity of the silicon epitaxial film was adjusted to 15 Ω · cm by adjusting the amount of B ₂ H ₆ . Also, as a reference sample, a silicon epitaxial wafer that has been epitaxially grown on a P ⁺ substrate with a normal electrical resistivity of 0.015 Ω · cm under the same conditions as the above silicon epitaxial wafer (hereinafter referred to as a normal silicon epitaxial wafer).
It was created.

Programmable read-only memory device (hereinafter referred to as PROM device) using both silicon epitaxial layers
And the device yields were compared. According to the invention
The yield of PROM devices was improved by 25% compared to PROM devices using ordinary silicon epi-wafer. This is considered to be due to the lower resistance of the P ⁺ substrate and the improvement of latch-up resistance and gettering ability due to the occurrence of misfit dislocations.

〔The invention's effect〕

As described above, the present invention provides sufficient latch-up by forming a device on a silicon epitaxial wafer having misfit dislocations caused by the difference in lattice constant between the P ⁺ substrate and the silicon epitaxial film.
It has α-ray soft error resistance, and the device yield could be higher than the conventional technology.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view for explaining a semiconductor device of the present invention, and FIG. 2 is a histogram showing the depth of misfit dislocation generation and an example of the relationship between the depth from the epitaxial wafer surface and the copper secondary ion intensity. Graph of actual measurement example,
FIG. 3 is a diagram showing the relationship between the resistivity ρ of the P ⁺ substrate and the critical epitaxial silicon film thickness hc at which misfit dislocations occur. 1 ... P ⁺ substrate, 2 ... misfit dislocation generation region, 3 ...
... Silicon epitaxial film, 4 ... Device formation region.

Claims (1)

[Claims] 1. A semiconductor device using a silicon epitaxial wafer in which a silicon epitaxial film is formed on a P type silicon substrate to which boron is added as an impurity element, wherein the electrical resistivity of the silicon epitaxial film is the P type silicon substrate. More than 100 times larger and the thickness of the silicon epitaxial film is h ≧ 0.57ρ
^1.38 (film thickness h: μm, electrical resistivity ρ of the silicon substrate:
^Satisfies the relationship of 10 ⁻³ Ω · cm, 1 ≦ ρ ≦ 30), and further h ≧
A semiconductor device having a thickness of 10 μm.