JPH0436653U - - Google Patents
Info
- Publication number
- JPH0436653U JPH0436653U JP7893390U JP7893390U JPH0436653U JP H0436653 U JPH0436653 U JP H0436653U JP 7893390 U JP7893390 U JP 7893390U JP 7893390 U JP7893390 U JP 7893390U JP H0436653 U JPH0436653 U JP H0436653U
- Authority
- JP
- Japan
- Prior art keywords
- data
- storage means
- information processing
- processing device
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Multi Processors (AREA)
- Retry When Errors Occur (AREA)
Description
第１図は、本考案の一実施例のデータ転送回路
の概略構成図である。
１……制御回路、２……データ線、３……送信
側の情報処理回路、４……受信側の情報処理回路
、５……第１のバツフア、６……第２のバツフア
、７……第３のバツフア、８……第４のバツフア
、９……比較回路、１０……ゲート。
FIG. 1 is a schematic diagram of a data transfer circuit according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Control circuit, 2... Data line, 3... Information processing circuit on the transmitting side, 4... Information processing circuit on the receiving side, 5... First buffer, 6... Second buffer, 7... ...Third buffer, 8...Fourth buffer, 9...Comparison circuit, 10...Gate.
Claims (1)
タ転送を行なうためのデータ転送回路において、 送信側の情報処理装置からデータを出力する出
力手段と、 出力したデータを記憶する第１の記憶手段と、 出力したデータを受信側の情報処理装置に転送
する第１のデータ転送手段と、 該第１のデータ転送手段より転送されるデータ
を記憶する第２の記憶手段と、 前記第１のデータ転送手段により転送されたデ
ータを送信側の情報処理装置に転送する第２のデ
ータ転送手段と、 該第２のデータ転送手段により転送されたデー
タを記憶する第３の記憶手段と、 前記第１の記憶手段のデータと、前記第３の記
憶手段のデータとを比較する比較手段と、 前記第３の記憶手段にてデータを記憶したとき
に、前記第２の記憶手段のデータを受信側の情報
処理装置に入力する入力手段と、 該入力手段を行なうときに、前記比較手段で前
記第１の記憶手段のデータと、前記第３の記憶手
段のデータとが同一でないときには、入力するデ
ータが誤りであると判断する手段とを備えるデー
タ転送回路。[Claim for Utility Model Registration] In a data transfer circuit for transferring data between information processing devices connected by a data line, an output means for outputting data from the information processing device on the sending side, and a memory for storing the output data. a first storage means for transferring the output data to a receiving side information processing device; and a second storage means for storing the data transferred from the first data transfer means. , a second data transfer means that transfers the data transferred by the first data transfer means to a transmitting side information processing device, and a third storage that stores the data transferred by the second data transfer means. means for comparing the data in the first storage means and the data in the third storage means; and when the data is stored in the third storage means, the second storage means an input means for inputting the data into a receiving side information processing device; and when performing the input means, the data in the first storage means and the data in the third storage means are not the same in the comparison means. and, in some cases, means for determining that input data is erroneous.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7893390U JPH0436653U (en) | 1990-07-24 | 1990-07-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7893390U JPH0436653U (en) | 1990-07-24 | 1990-07-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0436653U true JPH0436653U (en) | 1992-03-27 |
Family
ID=31622646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7893390U Pending JPH0436653U (en) | 1990-07-24 | 1990-07-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0436653U (en) |
-
1990
- 1990-07-24 JP JP7893390U patent/JPH0436653U/ja active Pending
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