JPH02145449U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a data transfer system according to one embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a memory switching circuit according to one embodiment, and FIG. FIG. 4 is a flowchart showing the processing operation of the transmitting CPU of the embodiment regarding data transfer, and FIG. 3 is a flowchart showing a processing operation regarding data transfer by a CPU on the receiving side. In the drawings, 10... CPU on the sending side, 12... CPU on the receiving side, 20, 22... RAM, 26... memory switching circuit, 36-50... gate buffer, 60,
64, 74, 76, 80...F/F, 82...Selector, 84, 86...Gate buffer.

Claims (1)

[Claims for Utility Model Registration] (1) In a system for transferring data from a transmitting microprocessor to a receiving microprocessor via a memory, first and second data can be written and read at any time.
a write end signal generated when the sending microprocessor finishes writing data to either the first or second memory; the first and second memories are alternately connected to one and the other of the transmitter and receiver microprocessors, respectively, in response to a read end signal generated when data has been read from either of the memories; means for generating a switching signal; and means for generating a signal indicating whether the first or second memory connected to the transmitting microprocessor is in a writable state at any time upon request from the transmitting microprocessor. and outputs a signal indicating whether the first or second memory connected to the receiving microprocessor is in a readable state at any time in response to a request from the receiving microprocessor. A data transfer system comprising means and. (2) In a system in which data is transferred from a transmitting microprocessor to a receiving microprocessor via a memory, the transmitting microprocessor is a first or a second microprocessor.
a write end signal generated when the receiving microprocessor finishes reading data from either the first or second memory; and a read end signal generated when the receiving microprocessor finishes reading data from either the first or second memory. a first logic circuit that outputs a signal indicating whether the first memory is in a writable state or a readable state in response to a write-end signal from the transmitting microprocessor; and a second logic circuit that outputs a signal indicating whether the second memory is in a writable state or a readable state in response to the read end signal from the receiving microprocessor. , in response to a write end signal from the sender microprocessor and a read end signal from the receiver microprocessor, the first and second memories are alternately read by the sender and receiver microprocessors. a third logic circuit that generates a switching signal for connection to one and the other of the microprocessors, respectively; and a third logic circuit that determines whether the first or second memory connected to the transmitting microprocessor is in a writable state. The output signal of the first or second logic circuit representing the first or second logic circuit is given in response to a request from the sending microprocessor, and is readable by the first or second memory connected to the receiving microprocessor. A memory switching circuit comprising: an output circuit that provides an output signal of the first or second logic circuit indicating whether the microprocessor is in a state in response to a request from the receiving microprocessor.