JPH0436670A - Electronic component testing device - Google Patents

Abstract

PURPOSE:To easily simulate the execution environment of the device to be measured and to improve the stability, clearness, repetitiveness, accuracy, and reliability of measurement by generating and measuring a signal in synchronism with one of digital input/output signals of mixed signal devices. CONSTITUTION:Local processes by pins of the device DUT 186 to be measured are performed by a GM modules (respective modules for signal generation and signal measurement and their common module), signal processor DSPs 123b which are controlled by a master sequencer MS112, etc. Then signals from the GM modules are preprocessed by the DSPs 123b, etc., and fed back to a host MS122 and a CPU 100. The DSPs 123b, etc., have dedicated buses mutually and are programmed so as to have a mutual communication, so their outputs can be processed mutually at a high speed. Further, the calculating processes of the DSPs 123b are carried out in synchronism with the same clock source with the MS122, etc., and the GM modules, so their outputs and operations are predictable, the reproducibility is secured, and the actual environment of the DUT 186 can be simulated stably and accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to the testing of electronic devices, and in particular to the testing of electronic devices, particularly mixed signal testing that uses many types of signals in various relationships.
) Related to electronic component testing equipment and electronic component testing methods suitable for testing equipment.

[Prior art and its problems]

Recent advances in electronic components can be seen in the diversity of their functions and improvements in performance while suppressing the increase in physical size. A conformal example is a large scale integrated circuit (LSI).

An explanation will be given below using an example of a test using an LSI as a device under test (DOT). Of course, the tests described are limited to smaller integrated circuits (ICs) and discrete components (transistors,
It can also be applied to testing PUTs, resistors, capacitors, inductors, etc.

A feature of recent LSIs is that they incorporate what used to be the peripheral circuits of the LSI, expanding their functions, and achieving faster speeds as the manufacturing process is improved. As a result, the human output signal of the LSI includes all direct current signals (DC), digital signals, and analog signals.

The time relationship between these input and output signals includes both synchronous and asynchronous signals, and the signal modulation rate is 100 MH2 or more. In this specification, these input/output signals are collectively referred to as mixed signals (++ixed signals). Conventional LS
I test equipment is often realized by expanding previous IC test equipment, and even those that are not are conceptually IC test equipment.
Many of them followed the test equipment. Therefore, L.S.
The basic idea was to divide the inside of I into functional blocks and conduct tests for each functional block.

For example, functional blocks that handle digital signals are tested in the same way as digital IC testers, and functional blocks that handle analog signals are tested in the same way as analog IC testers. An LSI that passes the tests of all functional blocks is determined to be a good product. Such a divide-and-conquer type test can be said to be an efficient system when the above-mentioned parts are highly independent, but when the independence between each functional block is low, as in recent LSIs, the LSI
This is not a test that guarantees operation in the actual usage environment.

For example, in the case of a high-speed analog-to-digital converter, simply evaluating the input/output conversion characteristics using direct current does not equate to evaluation in an actual usage environment. In a real environment, problems include the relationship between input signal frequency and conversion error, the relationship between input waveform and conversion error, and the relationship between input waveform and conversion clock and conversion error.

Furthermore, in the communication interface IC, data is input/output to a synchronous digital circuit while input/output is performed asynchronously, and analog signals may be received for input/output.

Digital filters also have analog input/output and internal digital circuits, and an analog-to-digital converter (ADC) and digital
Connected via an analog converter (DAC). Transfer function errors, noise, and spurious characteristics that depend on the relationship between the input signal and internal clock must be evaluated.

Furthermore, in testing an LSI that has an external feedback circuit, it is necessary to calculate and supply a control input immediately after measuring and evaluating a certain output signal. For example, there are many errors in ADCs.

Furthermore, when the results of calculations that combine the outputs of each bin of an LSI are used for evaluation, there is a problem that the calculation speed is slow. In a configuration in which a signal generation/signal measurement shared module (hereinafter simply referred to as GM module) and a signal processing module are connected via memory, data cannot be loaded into memory, calculation results stored, Communication has to be done through the intervention of a higher-level processing device or sequential communication of a signal processing device, which is slow and requires a complicated program for these procedures.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an electronic component testing apparatus that performs a test that simulates the actual usage environment of an electronic component under test that inputs and outputs mixed signals.

[Summary of the invention]

According to one embodiment of the invention, a test sequence (testseq
The sequencer controlling the GM module is configured in a hierarchical manner, and a long test series is executed without the intervention of a central processing unit.

The hierarchical configuration reduces wiring up to the l,M modules controlled by the lowest sequencer. That is, by providing some sequencers with memories and providing predetermined sequences therein, the amount of information to be transmitted through wiring can be reduced.

Specifically, in one embodiment of the present invention, the above sequencer and GM
All modules are configured to be synchronized by the same clock source, and desired input/output signals of the DOT can be synchronized.

In addition, by using multiple clock sources, the above sequencer and GM
When the modules are associated in time, the local coincidence of their waveforms is used to change the sequence within one effective minimum clock, so there is no latency or disruption of the sequence. Furthermore, it is also possible to perform pseudo asynchronous control by selecting the mutual frequencies of a plurality of clock sources in a rational ratio. In this case, the state control of the sequencer can also be executed within the next one clock period by detecting a matching point of clock edges.

By using a signal processing device i (referred to as DSP) together with the OM module controlled by the sequencer, the signal from the module is preprocessed by this DSP and fed back to the upper sequencer and central processing unit. Furthermore, since the DSPs have their own dedicated buses and can be programmed to communicate with each other, it is also possible to mutually process the DSP outputs at high speed. Since the communication of these DSPs and the calculation process accompanying the communication are performed in synchronization with the same clock source as those for the sequencer and 0M module, their outputs and operations are also predictable and reproducible. Therefore, stable and accurate simulation of the actual environment of OUT is possible.

In particular, it is characterized in that real-time testing of OUT can be performed easily.

[Embodiments of the invention]

FIG. 1 is a block diagram of an electronic component testing device (referred to as a tester) 1 according to an embodiment of the present invention, and FIG. 2 is a functional block diagram of a generalized model 2 of the component under test (OUT) 186 in FIG. 1. be.

The generalized model (referred to as GM) 2 is a general-purpose model of a mixed signal electronic component (referred to as DOT), and a model lacking some of its functional blocks is also eligible as a DUT in the present invention. The functional blocks of GM2 include a timing generator 21 that performs clock signal input/output and internal timing control, and a digital pattern interface (
(referred to as D-IP) 22, standardization of analog signal reception;
An analog circuit 26 and an analog-to-digital converter (referred to as ADC) 24 perform digitization, respectively, and a digital-to-analog converter (DAC) performs analogization of digital signals and standardization transmission of analog signals to output analog signals. ) 25, analog circuit 2
7, D-IP 22, ADC 24, and DAC 25, and a digital signal processing device (referred to as DSP) that performs input/output and processing of digital signals.

FIG. 1 shows the configuration of a tester 1. Each part indicated by a rectangle is realized by hardware, but it is also possible to realize it by software.

However, it is difficult to say that this is preferable because the speed becomes slower when -i is reached.

The tester 1 is programmed by a central processing unit (referred to as CPU) 100. A test sequence (referred to as test sequence TS) is programmed by cpuioo, and the necessary microprograms are sent to the sequencer 122.
132.143.153, etc., the test is performed by a mask sequencer (referred to as MSS) 122.
It is run independently of the central processing unit. Further, each subsystem 12, 13, 14, 15, 17, time measurement module 16, etc. all operate in synchronization with a clock signal supplied from a master clock (referred to as MCLK) subsystem (MCLK-5S) 11.

The configuration and operation of the tester 1 will be explained below.

Tester 1 is MCLK-3511, subsystem group (digital mask subsystem 12: DM-SS12
, Digital Slave Subsystem 13: DS
-SS13, waveform generator subsystem 14: WG
-SS14, waveform digitizer subsystem 15:
WD-SS15, time measurement module 16:7
MM16, DC subsystem 17: DC-8517
) and pin electronics and 0UT
186 and a test head 18 that interfaces with a group of subsystems.

MCLK-SSII inputs the DUT mask clock from the timing generator 21 of 0UT186 or DSP23 via the buffer 181, and outputs a first mask clock MCLK1 and a second mask clock MCI synchronized with the input. generate. The reference clock generator 111 that receives the output of the buffer 181 inputs outputs synchronized with the output to the first and second clock generators 112 and 113 to generate first and second mask clocks. M.C.L.
Both K1 and MCLK2 can be synchronized to the DUT master clock. Of course, if there is no DUT mask clock, if the DOT mask clock is not used, or if the reference clock generator is activated by another signal,
Even in the case of synchronization, it is easy to configure the system so that the reference clock can be generated.

Although MCLK 1 and MCLK 2 have different frequencies, it is preferable that their frequencies are selected in a rational ratio.

Timing handler 114 uses MCLK 1 and MCLK
A signal for controlling the mask sequencer (mask sequencer 122 in FIG. 1) of the tester 1 is generated.

For example, a mask sequencer sequence or test sequence is initiated.

The match uncertainty is ins in one embodiment.

DUT 186 typically includes a DM-SS 12 as a subsystem that provides signals to digital patterns and digital signal locks to define test sequences.

5S12 is a digital timing generator (DETG).
) 121, a mask sequencer 122 which outputs the programmed test sequence timed by the DETG 12, a vector memory 124a controlled by the mask sequencer 122, an engineering generator (termed EG) 124b, a formatter (FMT) It has a prior art DM-5S per pin resource (referred to as PPP) 124 that generates a digital signal for each pin of DUT 186 consisting of a is input.

Additionally, in one embodiment of the present invention, data processing resources 123
have. Data processing resources (referred to as DPR) 12
3 consists of a DSP 123b and a data memory 123a that stores data operated by the DSP 123b.

DPR 124 can change the output of DPR 12 by performing arithmetic processing on the test vector in vector memory 124a. Additionally, the DSP 123b can input and output data by communicating with other subsystems (for example, the DSP 133b of the DS-8S13.
3 is controlled by mask sequencer 122.

DS-5S13 has the same configuration as DM-5S12,
The slave sequencer 132 is the mask sequencer 12
The only difference is in place of 2. DGTG131, slave sequencer 132, DPR133, PPR1
34, data memory 133a, DSP133b,
Vector memory 134a, EG134b, FMT
I34c and pin driver 183a are each DGT
G121, master sequencer 122, DPR1
23. Correspondingly, perform similar operations.

Although the KG-5814 basically generates arbitrary waveforms using a well-known method, it has an internal DSP 144b and can perform calculations on stored waveforms and output them.

The WG-3S14 includes an AWG sequencer 143 that is timed by a timing generator 14GTG141, and a waveform generator 144 that generates a waveform according to a sequence stored in and output from the AWG sequencer 143. These constitute a per-channel resource (PCR) 142 that is normally prepared for the desired channels of the tester 1.

The waveform generation unit 144 performs waveform generation using the conventional technology, which is composed of a waveform memory 144a and a DAC 144C that converts its digital output into an analog waveform, and a DSP 144b that performs calculations on the waveform stored in the waveform memo 44a.
The waveform generation method according to the present invention can be implemented using 1440 inputs.

The output of WG-SS14 is 0U via output amplifier 184.
Applied to pin T186.

D-SS15, which operates in the opposite manner to WG-SS14, is D-SS15.
A signal is inputted from the signal output pin of the IJT 186 via the input amplifier 185, digitized by the ADC 154c, and then, if desired, subjected to calculations by the DSP 154b and stored in the waveform memory 154a. Its operation is controlled by digitizer sequencer 153. These constitute a PPR 134 prepared for desired channels. Timing control of the digitizer sequencer 153 is performed by a timing generator DTG 151.

Timing of each output of the 0UT 186 is performed by a conventional timing module 16. Timing control is performed by mask sequencer 122.

DC-SS17 is controlled by a timing generator DCTG171 which is controlled by mask sequencer 122.

At OUT, the DC characteristics of the CUT 186 are measured by the DC units 182b and 183b for each of the 186 digital input/output pins and the analog SMU 172. Conventionally, DC measurements were performed asynchronously by the central processing unit CP [1100, but in one embodiment of the present invention, they are performed synchronously by the mask sequencer 122. Therefore, all tests on the 0UT186, whose input and output are analog signals and whose internal operations include digital signal processing, are performed in synchronization with the digital signals, increasing the stability of the test and improving the reliability of the test. .

Each timing generator DGTG121, DETG131
, WGTG141, WDTG151, DCTG171
The clock supplied to the CPU 100 is set to either MCLK1 or LK2 by the central processing unit CPU100.

Even if the m master clocks are different among the subsystems, all the subsystems can be controlled completely at the same time by the control signal of the mask sequencer 122 clocked by the coincidence signal of the timing handler 114. Also,
If MCLK I, MCt, and K2 have different frequencies, asynchronous operation can be simulated in a pseudo manner.

The control signal of the mask sequencer 122 is introduced to the timing generator 131.141.151.171 of each subsystem and the slave sequencer 132.143.153 of each subsystem via the control line 122a as shown in FIG. and supports sequence block (referred to as SDK) based commands to these subsystems.

An example of SBK is shown below.

0S-5S13 Heh! :! Generation of a series of digital patterns and digital signals, generation of a series of waveforms to WG-SS14, WD-SS15
A series of waveform sampling, time measurement module 16
To one time measurement, DC-SS1? commands a series of voltage and current settings and measurements. In accordance with the instructions, the subsystem generates timing and sequence within the SBK in accordance with the internal microprogram and in synchronization with the mask clock used.

On the other hand, the end of the sub-sequence, the result of each DSP, the DU
The evaluation result of the output waveform of the TI 86 is immediately fed back to the mask sequencer 122 via the signal line 122b.

Response to commands from CPU 100, evaluation of returned signals, change of test sequence (program branching)
is determined to end within one cycle of the mask clock.
The change function is realized by hardware and is accelerated. This operating style is also applied to the execution of the sequencer block (SBK) of the subsystem and sequence changes based on the calculation results of the DSP. That is, mask sequencer 122 and slave sequencer 132.143.1.
53 can also be understood as executing a previously stored sequence by the CPU 100 and performing a master-slave operation.

Furthermore, since all changes in the execution of sequences within the sequencer are completed within one clock period, there is an advantage that no dead time occurs.

Figure 3 shows the waveform generator subsystem KG-SS14 and D
This is an example showing the relationship between the waveforms of M-SS12 or DS-SS13.

Programs 31.32 are mask sequences and slave
This is a software display showing each of the sequences, and an example of an actual waveform is shown in an actual waveform group 33.

33a shows the vector-7 address of DM-3S12 or 05-8S13, and 33b is the waveform of the clocked, formatted, and outputted vector of the vector address.

The sequence given from the mask sequencer 122
When block SBK is waveform 1 and waveform 2, the AWG sequencer generates a combination of waveform pieces ■, ■, ■, ■, ■ in order to synthesize waveforms 1 and 2 defined by SBK. 33c is the output of WG-5S14, 33d and 33
e shows the corresponding waveform pieces and waveforms used. A waveform without dead time is generated in synchronization with the digital vector.

Next, the DSPs 123, 133.144b, and 154b will be explained. The functions within these DSP subsystems have already been described.

These local DSPs can communicate with each other via a shared data path 19 independently of the CPU 100 and synchronously with the clock. It also sends and receives data from the CPU 100. The control command is transferred in advance from the CPU 100, and the operation is started by a synchronization command of the CPUloo or a synchronization signal of the sequencer of each subsystem. The DSP executes data input, operation, and output according to control instructions. Connection of the DSP to data bus 19 is also made by control commands or directly from CPU 100.

For example, by connecting the DSP154b and DSP144b to the data bus 19 and communicating with each other, the WD-8S15
The measurement results can be immediately fed back to the ws-ss 14 to change the waveform.

Furthermore, by having each DSP perform parallel processing, the processing speed decreases approximately in proportion to the number of parallel processing.

For example, there is an example in which the average of the output signals of each DUT pin is determined. Communication using data bus 19 can also be configured as a serial communication device.

Further, it is possible to speed up the Fourier transform by sampling the waveform at N points. Multiple channels of WD-8SI5 can be connected in parallel to reduce the sampling rate of each channel while increasing the final conversion rate.

When N=LxM, Discrete Fourier Transform (DFT) of L points
When calculating M pieces in parallel, (multiplying number of L point DFT) x
M+ (M-1) x (N/2) multiplications are required.

Also, the number of multiplications for L-point DFT is L2 when FFT is not used.
．． When FFT is performed with L being a power of 2 (L/2
) l o gz(L).

Therefore, as in the embodiment of the present invention, M=2 or M=4
If you choose, the number of multipliers will be (N/2) l o g2.
(N) , (N/2) I o gz(N) +
(N/2), and when performing distributed processing with two or four DSPs, the number of multiplications per device is reduced, and even if the data transfer time between DSPs is exceeded, it is possible to significantly shorten the time.

Note that the slave sequencer in the subsystem is configured to use a decoder and index register synchronized with the clock to designate the start address of the microprogram so as to activate the SBK in synchronization with the clock. Therefore, multiple branches can be performed within one clock cycle according to commands from the mask sequencer, and dead time is not introduced into the waveform due to branching. Tester 1 in one embodiment of the invention is 64 m as MCLKI, 2.
Hz-128mHz is used.

〔Effect of the invention〕

Implementation of the present invention produces the following effects.

1) The central processing unit only decodes and directs the execution of the test program and does not affect the progress of the test execution procedure. Therefore, test execution is not affected by the load on the central processing unit, and it is easy to simulate the execution environment of the DUT.

2) DC characteristic measurements, which were conventionally controlled by a central processing unit and operated asynchronously, are now performed by a mask sequencer in synchronization with other DUT signals, improving measurement stability and
Clarity and repeatability are improved.

3) Functional blocks of mixed signal equipment can be evaluated in parallel in an environment closer to the usage environment regardless of their type (analog, digital, synchronous, asynchronous), improving evaluation accuracy and reliability and reducing test time. is also shortened.

4) All subsystems are clocked by a synchronized mask clock, and each subsystem has a “next operation”
and "where to operate" are written in advance, and test programs can be created using a high-level language.

5) Synchronized decoders and index registers allow sequencer multiple branching and activation within one clock period, so there is no dead time in subsystem operation.

6) Since a multiple sequencer configuration is adopted, wiring is reduced in terms of hardware configuration.

7) Although it has a multiple sequencer configuration, all of them are synchronized, so parallel and independent operations of subsystems can be performed while maintaining good stability and repeatability.

8) By synchronizing each subsystem using multiple clocks synchronized with the DUT clock, it is possible to generate synchronous signals and simulate asynchronous operation by using the frequency difference between multiple clocks. and mixed synchronous and asynchronous D
The UT exam can be done in an integrated manner.

9) Local DSP for each subsystem or channel
It parallelizes signal processing and speeds up the overall test.

10) Local DSPs can communicate with each other and perform calculation processing and control of multiple DUT pin signals independently of the central processing unit, allowing complex input/output environments to be accurately clocked. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an electronic component testing apparatus according to an embodiment of the present invention. FIG. 2 is a functional block diagram of a generalized model of electronic components. FIG. 3 is a diagram for explaining an example of waveform generation according to the present invention. 100: Central processing unit 11: Mask clock subsystem (MCLK-
3S) 111: Reference clock generator 114: Timing handler 12: Digital mask subsystem (DM-8S)
) 122: Mask sequencer (MSS) 13: Digital slave subsystem (DS-8S) Two-waveform generator subsystem (WG-8S): Waveform digitizer subsystem (WD-3S) Two-time measurement module (TMM) ): DC subsystem (DS-8S) 18 Cotest head 186: Electronic device under test; device under test

Claims (1)

[Claims] A mixed signal device (referred to as an MSD) that performs signal generation and signal measurement in synchronization with one of the digital input/output signals of the device.
An electronic component testing device for testing the MSD, including a DC characteristic measurement subsystem.