JPH043694B2 - - Google Patents
Info
- Publication number
- JPH043694B2 JPH043694B2 JP18097484A JP18097484A JPH043694B2 JP H043694 B2 JPH043694 B2 JP H043694B2 JP 18097484 A JP18097484 A JP 18097484A JP 18097484 A JP18097484 A JP 18097484A JP H043694 B2 JPH043694 B2 JP H043694B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- switch means
- signal
- offset compensation
- compensation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】
本発明は符号器に使用されるオフセツト補償回
路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an offset compensation circuit used in an encoder.
符号器の直流オフセツトを補償するオフセツト
補償回路としては、一般に、サインビツト積分方
式の回路構成が採用されている。このサインビツ
ト積分方式オフセツト補償回路は、音声入力信号
における正および負の量が同じであることから、
符号器から出力されるサインビツトにより一定電
圧を加減して得られる電圧を符号器に負帰還して
オフセツト電圧を補償するよう動作する。上述の
一定電圧ΔVは、次式(1)のように、定電流源の電
流Ｉとパルス発生器のパルス幅ΔTと容量Ｃとか
ら生成する。 As an offset compensation circuit for compensating the DC offset of an encoder, a sine-bit integration type circuit configuration is generally adopted. This sine-bit integral type offset compensation circuit uses the same positive and negative amounts in the audio input signal, so
The voltage obtained by adding or subtracting a constant voltage using the sign bit output from the encoder is negatively fed back to the encoder to compensate for the offset voltage. The constant voltage ΔV described above is generated from the current I of the constant current source, the pulse width ΔT of the pulse generator, and the capacitance C, as shown in the following equation (1).
ΔV＝Ｉ・ΔT／Ｃ ……(1)
また、電源投入直後に大きなΔVを与えて高速に
オフセツト補償を行なうために定電流源の電流Ｉ
を大きくしている。 ΔV=I・ΔT/C...(1) In addition, in order to apply a large ΔV immediately after power is turned on and perform offset compensation at high speed, the current I of the constant current source is
is increasing.
この従来のサインビツト積分方式オフセツト補
償回路は、入力信号の正および負に追従して動作
するため入力信号の周波数に追従したゆらぎの発
生を避けられず、この結果、一回当りの補正量
ΔVを大きくすることができない。したがつて、
電源投入直後にはΔVが小さいためオフセツトを
補償しきれずに特性劣化を招くという欠点があ
る。 Since this conventional sine-bit integral type offset compensation circuit operates by following the positive and negative input signals, it is impossible to avoid the occurrence of fluctuations that follow the frequency of the input signal, and as a result, the correction amount ΔV per time is Can't make it bigger. Therefore,
Immediately after the power is turned on, ΔV is small, so the offset cannot be fully compensated for, resulting in characteristic deterioration.
本発明の目的は上述の欠点を除去したオフセツ
ト補償回路を提供することにある。 The object of the present invention is to provide an offset compensation circuit which eliminates the above-mentioned drawbacks.
本発明の回路は、符号器内で発生するオフセツ
トを補償するためのサインビツト積分方式オフセ
ツト補償回路において、それぞれの一方の端子が
正の電源および負の電源にそれぞれ接続された第
１および第２のスイツチ手段と、それぞれの一方
の端子が前記第１および第２のスイツチ手段の他
方の端子にそれぞれ接続されそれぞれの他方の端
子相互が接続された第１および第２の定電流源
と、一方の端子が前記第１および第２の定電流源
の他方の端子と接続され他方の端子が接地された
コンデンサーと、正電位レベルおよび負電位レベ
ルを有するサイン信号に応答して予め定めた幅を
有する正および負のパルスを出力するパルス発生
手段と、前記サイン信号および前記パルス発生手
段からの出力パルス信号のうちのどちらか一方を
それぞれ選択し選択した信号により前記第１およ
び第２のスイツチ手段の開閉動作をそれぞれ制御
する第３および第４のスイツチ手段と、電源投入
直後の予め定めた期間中には前記サイン信号を前
記第３および第４のスイツチ手段に選択させ該予
め定めた期間経過後には前記出力パルス信号を前
記第３および第４のスイツチ手段に選択させる制
御手段とを備えている。 The circuit of the present invention is a sine-bit integral type offset compensation circuit for compensating for offsets generated within an encoder. a switch means; first and second constant current sources, each of which has one terminal connected to the other terminal of the first and second switch means, and whose other terminals are connected to each other; a capacitor whose terminal is connected to the other terminal of the first and second constant current sources and whose other terminal is grounded; and a capacitor having a predetermined width in response to a sine signal having a positive potential level and a negative potential level. Pulse generating means for outputting positive and negative pulses, and either one of the sine signal and the output pulse signal from the pulse generating means are selected respectively, and the selected signal causes the first and second switching means to be switched on. third and fourth switch means for respectively controlling the opening and closing operations, and for causing the third and fourth switch means to select the sign signal during a predetermined period immediately after the power is turned on, and after the predetermined period has elapsed. and control means for causing the third and fourth switch means to select the output pulse signal.
次に本発明について図面を参照して詳細に説明
する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図を参照すると、本発明の一実施例は、そ
れぞれの一方の端子１２および１３が正の電源お
よび負の電源にそれぞれ接続された第１および第
２のスイツチ１０および１１と、それぞれの一方
の端子がスイツチ１０および１１の他方の端子１
４および１５にそれぞれ接続されそれぞれの他方
の端子相互が接続された第１および第２の定電流
源４および５と、一方の端子が定電流源４および
５の他方の端子と接続され他方の端子が接地され
たコンデンサー６と、端子１から与えられる正電
位レベルVDDおよび負電位レベルVSSを有するサ
イン信号に応答して予め定めた幅を有する正およ
び負のパルスを出力するパルス発生器２と、前記
サイン信号およびパルス発生器２からの出力パル
ス信号のうちのどちらか一方をそれぞれ選択し選
択した信号によりスイツチ１０および１１の開閉
動作をそれぞれ制御する第３および第４のスイツ
チ７および８と、電源投入直後の予め定めた期間
中には前記サイン信号をスイツチ７および８に選
択させ該予め定めた期間経過後には前記出力パル
ス信号をスイツチ７および８に選択させる制御回
路３とを備えている。 Referring to FIG. 1, one embodiment of the present invention includes first and second switches 10 and 11 with one terminal 12 and 13 of each connected to a positive power source and a negative power source, respectively; One terminal is the other terminal 1 of switches 10 and 11
4 and 15, respectively, and the other terminals of each of the first and second constant current sources 4 and 5 are connected to each other, and one terminal of the constant current sources 4 and 5 is connected to the other terminal of the constant current sources 4 and 5. A pulse generator that outputs positive and negative pulses having a predetermined width in response to a capacitor 6 whose terminal is grounded and a sine signal having a positive potential level V DD and a negative potential level V SS applied from the terminal 1. 2, and third and fourth switches 7 and 7, each selecting one of the sine signal and the output pulse signal from the pulse generator 2, and controlling the opening and closing operations of the switches 10 and 11, respectively, by the selected signal. 8, and a control circuit 3 which causes the switches 7 and 8 to select the sign signal during a predetermined period immediately after the power is turned on, and causes the switches 7 and 8 to select the output pulse signal after the elapse of the predetermined period. We are prepared.
電源投入直後の予め定めた期間中において、制
御回路３は、端子１からのサイン信号を選択する
ようスイツチ７および８を切り換える。スイツチ
１０はスイツチ７からの出力信号の電圧がVDDの
とき閉じ、この結果、電流源４はコンデンサー６
を正方向に充電する。また、スイツチ１１はスイ
ツチ８からの出力信号の電圧がVSSのとき閉じ、
この結果、電流源５はコンデンサー６を負方向に
充電する。すなわち、前記期間中、制御回路３に
より、端子１からのサイン信号はオフセツト電圧
のみに追従する信号となつており、オフセツトを
補償するに必要な電圧が出力端子９から出力され
る。 During a predetermined period immediately after power is turned on, control circuit 3 switches switches 7 and 8 to select the sine signal from terminal 1. Switch 10 closes when the voltage of the output signal from switch 7 is V DD , so that current source 4 is connected to capacitor 6
Charge in the positive direction. Further, switch 11 closes when the voltage of the output signal from switch 8 is V SS ;
As a result, current source 5 charges capacitor 6 in the negative direction. That is, during the period, the control circuit 3 makes the sine signal from the terminal 1 a signal that follows only the offset voltage, and the voltage necessary to compensate for the offset is output from the output terminal 9.
電源投入時から予め定めた期間経過すると、制
御回路３は第２図ｂに示すようなパルス発生器の
出力を選択するようスイツチ７および８を切り換
える。この結果、以後、従来のサインビツト積分
方式オフセツト補償回路と同じオフセツト補償動
作を行なう。 After a predetermined period of time has elapsed since the power was turned on, the control circuit 3 switches the switches 7 and 8 to select the output of the pulse generator as shown in FIG. 2b. As a result, the offset compensation circuit performs the same offset compensation operation as the conventional sine-bit integral type offset compensation circuit.
以上、本発明には、電源投入直後の特性劣化を
除去できるという効果がある。 As described above, the present invention has the effect of being able to eliminate characteristic deterioration immediately after power is turned on.
第１図は本発明の一実施例を示す回路図、第２
図ａは端子１に与えられる信号を示す図および第
２図ｂは発生器２の出力信号を示す図である。
図において、１……入力端子、２……パルス発
生器、３……制御回路、４……定電流源、５……
定電流源、６……コンデンサー、７，８……切換
えスイツチ、９……出力端子。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
Figure a shows the signal applied to terminal 1, and Figure 2b shows the output signal of generator 2. In the figure, 1... input terminal, 2... pulse generator, 3... control circuit, 4... constant current source, 5...
Constant current source, 6... Capacitor, 7, 8... Changeover switch, 9... Output terminal.
Claims (1)
めのサインビツト積分方式オフセツト補償回路に
おいて、それぞれの一方の端子が正の電源および
負の電源にそれぞれ接続された第１および第２の
スイツチ手段と、それぞれの一方の端子が前記第
１および第２のスイツチ手段の他方の端子にそれ
ぞれ接続されそれぞれの他方の端子相互が接続さ
れた第１および第２の定電流源と、一方の端子が
前記第１および第２の定電流源の他方の端子と接
続され他方の端子が接地されたコンデンサーと、
正電位レベルおよび負電位レベルを有するサイン
信号に応答して予め定めた幅を有する正および負
のパルスを出力するパルス発生手段と、前記サイ
ン信号および前記パルス発生手段からの出力パル
ス信号のうちのどちらか一方をそれぞれ選択し選
択した信号により前記第１および第２のスイツチ
手段の開閉動作をそれぞれ制御する第３および第
４のスイツチ手段と、電源投入直後の予め定めた
期間中には前記サイン信号を前記第３および第４
のスイツチ手段に選択させ該予め定めた期間経過
後には前記出力パルス信号を前記第３および第４
のスイツチ手段に選択させる制御手段とを備えた
ことを特徴とするオフセツト補償回路。1. In a sine-bit integral type offset compensation circuit for compensating for offsets occurring in an encoder, first and second switch means each having one terminal connected to a positive power supply and a negative power supply, respectively; first and second constant current sources, one terminal of which is connected to the other terminal of the first and second switching means, and whose other terminals are connected to each other; and a capacitor connected to the other terminal of the second constant current source and having the other terminal grounded;
pulse generating means for outputting positive and negative pulses having predetermined widths in response to a sine signal having a positive potential level and a negative potential level; third and fourth switch means each select one of them and control the opening/closing operations of the first and second switch means by the selected signal; the third and fourth signals
After the predetermined period has elapsed, the output pulse signal is switched to the third and fourth switch means.
1. An offset compensation circuit comprising control means for causing the switch means to select the offset compensation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18097484A JPS6158324A (en) | 1984-08-30 | 1984-08-30 | Offset compensating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18097484A JPS6158324A (en) | 1984-08-30 | 1984-08-30 | Offset compensating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6158324A JPS6158324A (en) | 1986-03-25 |
| JPH043694B2 true JPH043694B2 (en) | 1992-01-24 |
Family
ID=16092531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18097484A Granted JPS6158324A (en) | 1984-08-30 | 1984-08-30 | Offset compensating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6158324A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03205921A (en) * | 1990-01-08 | 1991-09-09 | Hitachi Denshi Ltd | Digitizer circuit |
| JPH04134121U (en) * | 1991-05-28 | 1992-12-14 | 古河電気工業株式会社 | electrical junction box |
-
1984
- 1984-08-30 JP JP18097484A patent/JPS6158324A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6158324A (en) | 1986-03-25 |
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