JPH043703B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a conversion device that obtains addition/subtraction pulse width conversion outputs of a plurality of binary value data.

(Prior Art) It is widely practiced in the field of numerical control to pulse-width convert the results of addition and subtraction of a plurality of numerical data, usually represented by binary codes, to obtain a control signal. Conventionally, a pulse width conversion device for generating this control signal is roughly divided into three circuit sections. That is, it consists of an addition/subtraction result detection circuit section that detects the addition/subtraction results of a plurality of numerical data, a storage circuit section that temporarily stores the detection results, and a pulse width modulation circuit section that reads out the stored contents and performs pulse width modulation. has been done. Pulse width conversion devices that have multiple circuit sections require wiring to connect the individual circuit sections, making the device configuration itself complex and of course slowing down the response speed. It has a fatal flaw.

(Problems to be Solved by the Invention) In view of the above-mentioned drawbacks of the conventional pulse width conversion device, it is an object of the present invention to directly convert the pulse width of the addition/subtraction results of a plurality of numerical data represented by binary codes. An object of the present invention is to provide a pulse width conversion device that can perform the following steps.

(Means for Solving the Problems) The pulse width conversion device of the present invention converts a plurality of numerical data, each represented by an n-bit binary code, into 2 ⁿ bits.
A numerical data switching circuit that sequentially selects and outputs data at a bit cycle, and n control signals whose logic levels are inverted every ²⁰ to 2n ^-1 bits together with the numerical data selectively output from this numerical data switching circuit. Each logic level of the least significant bit to the most significant bit of the n-bit numerical data received and selectively outputted, and each logic of the n control signals whose logic level is inverted every ²⁰ to ^2n-1 bits. a signal generating circuit that generates a response signal when all the levels match, and a signal generating circuit that generates a first logic level at the start of the ^2n- bit period when the selectively outputted numerical data is the numerical data to be added; It is inverted to a second logic level in synchronization with the response signal from the signal generation circuit, and when the selectively outputted numerical data is the numerical data to be subtracted, the
2 circuit means for outputting a pulse signal that takes the second logic level at the start of ^{a n-bit} period and inverts to the first logic level in synchronization with the response signal from the signal generation circuit. shall be.

Preferably, the circuit means is a first means having an output terminal to which the pulse signal is output, and first and second input terminals, and the circuit means is a first means having an output terminal to which the pulse signal is output, and a first means and a second input terminal. first means for holding at said first logic level and said output terminal at said second logic level by providing a signal to said ^second input terminal; a second means for generating a start signal; and when the selected output numerical data is numerical data to be added, the start signal is input to the first input terminal of the first means, and the response signal is input to the first input terminal. 1 respectively to the second input terminals of the first means, and when the selectively output numerical data is the numerical data to be subtracted, the start signal is supplied to the second input terminal of the first means in response to the response. and third means for respectively providing a signal to the first input terminal of the first means.

(Effects of the Invention) According to the present invention, a plurality of pieces of numerical data are sequentially pulse width modulated with a period of ²ⁿ bits, and each piece of numerical data is equal to the data content and has a relationship of opposite levels to each other corresponding to addition or subtraction. Since it is converted into a pulse width ^modulation signal with a pulse width of A width modulated signal is arranged. For example, if there are 4 numerical data A, B, C, and D, and you want to obtain a pulse width conversion output corresponding to the numerical values A-B-C+D, the first numerical data A is a high level equal to its contents. The next two numerical data B and C each have a low level pulse width equal to their contents, and the last numerical data D has a high level pulse width equal to its contents. Therefore, within one conversion cycle of 2 ⁿ × 4 bits, a pulse width modulated signal consisting of a number of high level bits equal to the content of numerical data A, and two pulse width modulated signals consisting of high level bits obtained by subtracting a number of low level bits equal to the content of each of numerical data B and C from 2 ⁿ bits;
A pulse width modulated signal array consisting of a number of high level bits equal to the content of the numerical data D is produced. That is, if we focus only on the high level bits, A + (2 ⁿ - B) + (2 ⁿ - C) + D = 2 ⁿ ×2 +
It is converted and output as a signal having a pulse width corresponding to the numerical value of (A-B-C+D). Therefore, m
In the ^case of numeric data of
A pulse width converted output having a high level period of . However, TU is the pulse width of unit bit.

Of course, it is also possible to provide a pulse width conversion output focusing only on low level bits. The individual modulation signals of the numerical data and the arrangement within the modulation period can all be easily combined into one circuit configuration using simple known logic circuits, so the device has a simple configuration and is highly resistant to changes in data content. A pulse width conversion device that can respond quickly can be realized. The present invention will be described in detail below with reference to the drawings.

(Example) FIG. 1 is a block configuration diagram explaining the present invention.
The case where it was implemented on four numerical data is shown. In this embodiment, a numerical data switching circuit 1 sequentially inputs n-bit binary numerical data A, B, C, and D at a cycle of 2 ⁿ bits, detects the numerical data contents, and outputs respective numerical data content response signals pa, pb. , pc and
Numerical data content response signal generation circuit 2 that generates PD, and an output level state holding circuit that inverts the level each time each numerical data content response signal is input, holds the state, and outputs a pulse width conversion signal array Y for each numerical data. 3. Prior to pulse width modulation of individual numerical data, the output level is set to high level for numerical data to be added and to low level for numerical data to be subtracted, corresponding to the desired addition/subtraction of numerical data. In addition to presetting the output level of the state holding circuit 3, it also includes a control signal system Ck that controls the operation of all the circuits.

Numerical data content response signals pa, pb, pc and pd
is a pulse signal having a pulse width of unit bit TU, which is generated when the numerical data switching circuit 1 detects the sum of the weighted logical values of each bit of the numerical data A, B, C, and D input sequentially. be. These drive the output level state holding circuit 3, which is preset to high or low levels for desired additions and subtractions, and inverts the output level when the sum of the weighted logical values of each bit is detected. Therefore, in the case of addition numerical data, a pulse width modulated signal with a high level period with a bit width equal to the sum of the weighted logical values of the bits, and in the case of subtraction numerical data, the pulse width modulated signal has a high level period equal to the sum of the weighted logical values of the bits. Pulse width modulated signals each having a low level period of bit width equal to the weighted sum are output. Therefore, within a conversion period obtained by multiplying 2 ⁿ bits by the number of numerical data, that is, by 4, pulse trains of pulse width modulated signals of these four numerical data are arranged and output as a pulse width conversion output Y.

A known coincidence detection circuit is used to detect the output point of the sum of the weighted logical values of the bits, and a similarly known R-S is used for the output level state holding circuit.
Since a latch circuit can be used, the device configuration is extremely easy.

2 and 3 are a connection circuit diagram and a time chart showing an embodiment of a conversion device in which the present invention is applied to four numerical data of 3-bit configuration. In this embodiment circuit, the numerical data switching circuit 1 inputs numerical data A (a ₃ , a ₂ , a ₁ ), B (b ₃ , b ₂ ,
AND circuits 4 to 1 arranged corresponding to each input bit of b ₁ ), C (c ₃ , c ₂ , c ₁ ), and D (d ₃ , d ₂ , d ₁ )
5, NOR circuits 16 to 18, NOR circuit 1
The numerical data content response signal generation circuit 2 is composed of a match detection circuit consisting of exclusive NOR circuits 22 to 24 and a NOR circuit 25, and an output level state holding circuit. 3 is constituted by an R-S latch circuit consisting of NOR circuits 26-29. Also, the control signal system
Ck consists of six control signals Ck ₀ to Ck ₅ , including negative logic circuits 30, 31, 36 to 39, 41 and 4.
5. The control circuit 4 is constituted by NAND circuits 32-35 and NOR circuits 40, 42-44. Here, the control signal Ck ₁ is applied within each modulation period Ta, Tb, Tc, and Td of the numerical data.
It has a period of ²⁰ bits, and Ck ₂ to Ck ₅ are each
It is set to have a bit period of 2 ¹ , 2 ² , 2 ³ and 2 ⁴ , and Ck ₀ is set to be a continuous pulse signal having a width of 1/2 of the unit bit pulse width TU.
Of the six control signals, Ck ₄ and Ck ₅ are used as gate control signals for the numerical data switching circuit 1, and together with Ck ₀ , the output level of the output level state holding circuit 3 is set to high or high in advance in accordance with the desired addition/subtraction. Generates a set/reset signal to set each level to low. The remaining three Ck ₁ , Ck ₂ and Ck ₃
The two control signals drive the numerical data content response signal generation circuit 2 to generate numerical data content response signals pa, pb, pc, and pd at the time of detection of the sum of weighted logical values of each bit of numerical data. act.

This example circuit is expressed as numerical data A, B, C and D.
Regarding, since the wires are connected to obtain the pulse width conversion output Y ₁ of the addition/subtraction result of A-B-C+D,
The circuit operation will be explained below based on this.

The time chart in Figure 3 shows numerical data A, B, C and D (110), (100), respectively.
The signal waveforms of the circuit when (011) and (101) are explained, and the input timings of the set/reset signals S ₁ , R ₁ and S ₂ , R ₂ that drive the R-S circuit and the addition/subtraction results " The pulse arrangement of the pulse width conversion output Y ₁ for "4" is shown. The reset signal _R1 is generated when the sum of the weighted logical values of the bits of the addition numerical data A and D is detected, respectively, and inverts the output level of the R-S latch circuit from high to low to set the modulation period Ta and
Arrange pulse width modulated signals with high level periods of 6Tu and 5Tu equal to their respective data contents within Td. Further, the set signal _S1 is generated when the sum of the weighted logical values of the bits of the subtracted numerical data B and C is detected, and it inverts the output level of the R-S latch circuit from low to high, and sets the modulation period Tb. and pulse width modulated signals with low level periods of 4Tu and 3Tu equal to their respective data contents within Tc. Therefore, the numerical data A, B, C and D are contained within the entire conversion period T.
The pulse width conversion signal array Y ₁ having a high level period of 20 Tu corresponds to the addition/subtraction result "4" and is output. Then set/reset signal
S ₂ and R ₂ are completely unrelated to the above-mentioned S ₁ and R ₁ , and are the states of the output levels of the R-S latch circuits generated at the time of detection of the sum of the weighted logical values of the bits of each numerical data. This is a setting signal. That is, the set signal S ₂ is generated at the start of detection of the sum of the weighted logical values of the bits of the added numerical data A and D, and the set signal S _{2 is}
The output level of the R-S latch circuit is always set to high level before the input of the reset signal.
R ₂ is generated at the start of detection of the sum of the weighted logical values of the bits of the subtraction numerical data B and C, and similarly, the output level of the R-S latch circuit is generated before inputting the signals S ₁ and R ₁ . Always low
It acts to set the level. These set/reset signals S ₁ , R ₁ and S ₂ , R ₂ can be easily generated using control signals Ck ₀ to _{Ck 5} .

In the connection circuit diagram of FIG. 2, the control signals Ck ₄ ,
Ck ₅ and its negation signal are connected to the NAND circuit 32~
35 is driven to sequentially output one of them, and the outputs of the AND circuits 4 to 15 are gated. When the NAND circuit 32 outputs, the AND circuits 4, 8 and 12 are gated simultaneously, and the numerical data A (a ₃ , a ₂ ,
Each bit of _a1 ) is input. NAND circuit 3
When 3 is output, AND circuits 5, 9 and 13
are gated at the same time, numerical data B (b ₃ , b ₂ , b ₁ )
Each bit is input. Similarly, when the NAND circuits 34 and 35 respectively output,
Numerical data C and D are respectively input. The bits of each numerical data input in this way are input to a coincidence detection circuit consisting of negative exclusive OR circuits 22 to 24 and negative AND circuit 25, and the sum of the weighted logical values of each bit is calculated. When detected, the NAND circuit 25 outputs a numerical data content response signal representing the content of each numerical data.
pa, pb, pc and pd are output respectively. (Not shown in Figure 2). On the other hand, when either the addition numerical data A or D is selected and input, the negative output of the selection signal is output from the negative OR circuit 40, and the R-S latch is output together with the numerical data content response signal pa or pd. It is input to the NOR circuit 26 of the circuit. Here, since the levels of the negative output of the numerical data content response signal and the selection signal are both "0", the output level of the negative OR circuit 26, that is, the input level of the reset signal _R1 of the R-S latch circuit is "1". ”. At this time, the NOR circuit 27 receives a numerical data content response signal.
Since the same level "1" as the selection signal is input together with the "0" level of pa or pd, the set signal S ₁
The input level of indicates "0". Furthermore, when either subtraction numerical data B or C is selected and input, the circuit operation is completely opposite to that described above, and the level of the reset signal _R1 becomes "0".
A level of "1" appears in the set signal _S1 .

Further, the control signal Ck ₀ is inputted to the NOR circuit 44 together with Ck ₁ to Ck ₃ . Control signal Ck ₀ is 1/2Tu
Since it is a continuous pulse signal with a pulse width of , each modulation period Ta,
The negative logic circuit 45 outputs level "0" only at the start time of each modulation operation within Tb, Tc and Td. This output level "0" is the negation of the input selection signal of the numerical data mentioned above and the reset signal _R1.
It is input to the NOR circuit 42 together with the output of .
At the start of each modulation of numerical data, the detection operation of the sum of the weighted logical values of the bits has not yet been completed, so the reset signal _R1 remains at the "0" level. Therefore, when either the addition numerical data A or D is selected and input, all three inputs of the NOR circuit 42 are at the "0" level, and a set signal at the level "1" is output from the output side. S ₂ is output. At this time, the level "1" that has been negated again via the NOR circuit 41 is input to the other NOR circuit 43, so the level of the reset signal R2 is " ₁ " regardless of the other input levels. 0". Furthermore, when either subtraction numerical data B or C is selected and input, the NOR circuits 42 and 43 perform completely opposite circuit operations and set the level of the reset signal R1 to " ₁ ".
Then, the set signal _S2 is output as a "0" level.

The above has explained the case where the addition/subtraction results of A-B-C+D are pulse-width modulated for the numerical data A, B, C, and D. However, if the input connection of the NOR circuit 40 is changed, the addition/subtraction results of all the combinations can be obtained. The pulse width conversion output Y can be obtained.

The pulse width conversion output Y obtained at this time is
One conversion period is 32Tu, and the high level period is {16
+(addition/subtraction result)}It is equipped with a pulse train of Tu.

Also, if there are m numerical data, the conversion period is
8mTu, and for l subtracted numerical data,
{8l+(addition/subtraction result)} has a high level period of Tu.

Furthermore, it is clear that it can be implemented in the case of n-bit numerical data, in which case 2 ⁿ ·
Let mTu be the conversion period, and the high level period {2 ⁿ・
A pulse width conversion output having a pulse train of l+(addition/subtraction result)}Tu can be obtained.

As explained in detail above, according to the present invention,
Since it is possible to obtain a pulse width conversion device configured in one circuit using a simple logic circuit, it can be assembled into a small-chip semiconductor device that responds extremely quickly to changes in data content.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram explaining the present invention, and FIGS. 2 and 3 are connection circuit diagrams showing an embodiment of a conversion device when the present invention is applied to four numerical data of 3-bit configuration. This is a time chart. 1... Numerical data switching circuit, 2... Numerical data content response signal generation circuit, 3... Output level status holding circuit, 4... Control circuit, A (a ₃ , a ₂ , a ₁ ), B
(b ₃ , b ₂ , b ₁ ), C (c ₃ , c ₂ , c ₁ ), D (d ₃ , d ₂ , d ₁ )
... Numerical data, Ck ₀ to Ck ₅ ... Control signal, R ₁ ,
_R2 ...Reset signal, 25, 32-35...NAND circuit, _S1 , _S2 ...Set signal, 4-15
...Logic product circuit, 16-18, 26-29, 4
0,42-44...NOR circuit, 22-24
...Negative exclusive OR circuit, 19-21, 36-
39, 41, 45...Negation logic circuit, pa, pb,
pc, pd...Numerical data content response signal, Y...Pulse width conversion output.

Claims (1)

[Claims] A numerical data switching circuit that sequentially selects and outputs a plurality of numerical data each represented by a binary code of 1 n bits at a cycle of 2 ⁿ bits, and a numerical data selectively output from the numerical data switching circuit. 2 ⁰ with data
to 2 ^n-1 bits, each of which receives n control signals whose logic level is inverted for every n-1 bit, and which is selectively outputted.
Each logic level of the least significant bit to the most significant bit of the bit numerical data and each logic level of the n control signals whose logic levels are inverted every ²⁰ to 2n ^-1 bits are all matched. When the selected output numerical data is the numerical data to be added, the signal generating circuit generates the response signal, and when the selected output numerical data is the ^numerical data to be added, the signal generating circuit generates the response signal.
and inverts it to a second logic level in synchronization with the response signal from the signal generation circuit;
When the selected output numerical data is numerical data to be subtracted, the second logic level is set at the start of the 2 ⁿ bit period, and the first logic level is set in synchronization with the response signal from the signal generating circuit. and circuit means for outputting a pulse signal whose level is inverted. 2. The circuit means is a first means having an output terminal to which the pulse signal is output, and first and second input terminals, and the circuit means outputs the output terminal by supplying the signal to the first input terminal. first means for holding the output terminal at the first logic level and holding the output terminal at the second logic level by providing a signal to the second input terminal; and a start indicating the beginning of the 2 ⁿ -bit period. a second means for generating a signal; and when the selectively output numerical data is numerical data to be added, the start signal is input to the first input terminal of the first means, and the response signal is input to the first input terminal of the first means. and when the selected output numerical data is numerical data to be subtracted, the start signal is supplied to the second input terminal of the first means, and the response signal is supplied to the second input terminal of the first means. and third means for respectively supplying the first input terminals of the first means to the first input terminals of the first means.
Pulse width conversion device as described in .