JPH04371014A - Latch circuit - Google Patents

Abstract

PURPOSE:To reduce the number of control lines. CONSTITUTION:A clock and strobe generating circuit 3 is provided which generates a shift-in clock S9 for data to a shift register 1 and a strobe S7 for data transfer from the shift register 1 to a register 2 based on a clock and data. That is, the operation of the shift-in clock S9 is started when data is in the low level at the time the rise of clock and is in the high level at the time the fall of clock and it is stopped and the strobe S7 for data transfer is outputted when data is in the high level at the time the rise of clock and is in the low level at the time the fall of clock. Thus, it is unnecessary to provide a strobe line.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit used in electronic equipment and the like.

0002

[Prior Art] Conventionally, a serial latch circuit inputs data one bit at a time in synchronization with a clock, temporarily stores this data in a buffer such as a shift register, and then transfers the data in the buffer to a register using a strobe signal. There are some things that I decided to transfer and keep.

As an example, a conventional latch circuit for latching 8-bit data is shown in FIG. Data is serially transferred bit by bit according to the clock timing to the shift register 10.
0, and when the input data reaches 8 bits, it is input to the register 110 in parallel with 8 bits as one unit. Further, FIG. 6 shows an example in which a D-type flip-flop circuit (hereinafter referred to as "D-FF") is used in the register 110 shown in FIG. 4. In FIG. 6, the conventional latch circuit includes a shift register 100 consisting of eight D-FFs 101 to 108 that input a clock to a clock terminal CK, input data and the Q output of the previous stage to a terminal D, and a strobe to the clock terminal CK. Input the signal and shift register 100
Eight D-FFs 111 to 118 input the Q outputs of each D-FF 101 to 108 to terminal D, and each D-FF1
The register 110 includes inverters 121 to 128 that invert the Q outputs of the transistors 11 to 118.

As shown in the timing chart of FIG. 5, this latch circuit shifts data into the shift register 100 one bit at a time at each rising edge of the clock, and when the data has been shifted in by 8 bits, the rising edge of the strobe The contents of shift register 100 are transferred to register 11 by
The latched data is latched to 0, and the latched data is output to this register 110 in parallel.

[0005]

However, the aforementioned latch circuit requires three control lines: a data line, a clock line, and a strobe line. On the other hand, it is better to have fewer control lines, and if pulse noise is applied to the clock line, this noise may be used as a clock to shift incorrect data into the shift register, and furthermore, pulse noise may be applied to the strobe line. Then, the data in this erroneous shift register is latched and output.

[0006]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a clock for taking in data to a buffer and a strobe for permitting transfer from the buffer to a register based on the rising and falling edges of the clock and data. We have provided a means to generate it. In this case, the condition may be that the logic levels of data at the rise and fall of the clock are different.

[0007]

[Operation] Since the clock and strobe for shift-in are generated based on the clock and data, only two lines, a clock line and a data line, can be used, and there is no need to provide a control line. Furthermore, by setting the condition that the logic levels of data at the rising edge and falling edge of the clock are different, it is possible to reduce the influence of noise.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of an example of a latch circuit according to the present invention, FIG. 2 is a circuit diagram of an example of a fall detection circuit of the latch circuit, and FIG. 3 is a timing chart showing the operation of the latch circuit.

In FIG. 1, the latch circuit according to the present invention includes a shift register 1 which is a buffer for storing data, a register 2 which takes in and holds the data stored in the shift register 1, and a register 2 which is a buffer for storing data and a clock. A data capture clock input to the clock terminal CLK of the shift register 1 and a clock terminal C of the register 2.
The clock strobe generation circuit 3 generates a data transfer permission strobe input to LK. Note that shift register 1 and register 2 have the same configuration as a conventional register (see FIG. 6).

The clock strobe generation circuit 3 has D-
A clock is input to the clock terminal CLK of FF11, data is input to terminal D, and the exclusive-OR circuit (
Hereinafter referred to as "EX-OR". ) 12 directly inputs data and the Q output of the D-FF 11. Data is directly input to the AND circuit (hereinafter referred to as "AND") 13, and the data is inputted directly to the D-FF 1 through the inverting circuit 14.
The Q output of D-FF 11 is input to the AND 15, and data is input to the AND 15 via the inverting circuit 16, and the Q output of the D-FF 11 is directly input.

On the other hand, the clock is input to a falling edge detection circuit 17 to detect the falling edge of the clock. As shown in FIG.
AND21 the signal inverted by
and outputs pulse S4 at the falling edge of the clock.

Then, the pulse S1 obtained by inverting the output of EX-OR12 by the inverting circuit 12a is applied to AND23.
The output pulse S2 of 3 is input to AND24, the output pulse of AND15 is input to one of AND25, and
The pulse S4 from the fall detection circuit 17 is input to the other terminals 3 to 25, respectively.

Furthermore, the output pulse S6 of AND24 is
It is input to the set terminal S of the R-type flip-flop circuit 26 (hereinafter referred to as "S-RFF"), and the output pulse of AND25 is input to the reset terminal R of the S-RFF 26, which is the Q output of this S-RFF 26. Pulse S8 and AND2
3 output pulse S5 is input to AND27, and this A
The output of the ND27 is inputted to the clock terminal CLK of the shift register 1 as a clock. Further, the output pulse S7 of the AND25 is inputted to the clock terminal CLK of the register 2 as a strobe.

In the latch circuit configured as described above, based on the data and the clock, (1) the data is at a high level (hereinafter referred to as "
"H level". ), the logic is "1"; (2) If the data is at a low level at both the rising and falling edges of the clock (hereinafter referred to as "L level"), the logic is "0".
, (3) If the data is at L level when the clock rises and the data is at H level when the clock falls, "data start". (4) When the data is at H level when the clock rises,
If the data is at L level at the falling edge of the clock, it is assumed that the data is transferred to the register (strobe) at the end of the data. Note that data start means subsequent data (logical 1 or 0)
This means the start of shift-in, and no shift-in is performed before this or after the end of data.

As shown in FIGS. 3(a) and 3(b), the operation of this latch circuit is such that when data and clocks are input, the period T0 to T1 is "data start", and the period T1 to T1 is "data start".
2 is the shift in of 8-bit data (D0 to D7), and the period T2 to T3 is the transfer to the register when the data ends.
The output pulses S1 to S9 of each section at this time are as shown in FIGS.

[0016] Here, when data is input, AND
When the pulse S4 outputted from the falling edge detection circuit 17 is inputted at the falling edge of the clock, a pulse S6 is outputted from the AND 24 which inputs the pulse S2 outputted from 13, that is, at the "start of data", The S-RFF26 is set by this pulse S6, and the pulse S8 becomes "H" until the "end of data", thereby EX-
AND2 using the output pulse S1 of OR12 as the gate signal
From 3 onwards, a pulse S5 is output every time the clock falls, and this pulse S5 is inputted to the shift register 1 as a data acquisition clock S9 via an AND 27, and data is acquired.

Furthermore, an AND 15 inputs data via the inversion circuit 16 and inputs the Q output of the D-FF 11.
The output pulse S3 becomes "H" at the falling edge of data and becomes "L" at the rising edge of the clock, so this pulse S3 becomes "H" at the falling edge at the end of the data, and no clock is input after that. Continue that state by AND
25 is opened, the pulse S4 is output from the AND 25 as a pulse S7 at the falling edge of the last clock and is input as a strobe to the register 2, and data is transferred from the shift register 1 to the register 2.

In this case, the pulse S8, which is the Q output of the S-RFF 26, is held at the H level from "data start" to "data end", and the clock is not input to the shift register 1 during other periods. This serves as a gate signal for the clock line, thereby preventing the problem of external noise from entering the clock line. That is, at times other than data input (before T0 and after T3 in FIG. 3), pulse S8 is set to the "start of data" (the condition that data is at L level at the clock rise and data is at H level at the clock fall). Unless they are aligned, they remain at L level, so a clock for data capture to the shift register is generated and no data is captured.

[0019] Furthermore, when noise enters the clock line, the condition for "starting data" is that the data must be at the L level at the rising edge of the clock and at the H level at the falling edge of the clock. Since the pulse is a typical pulse, the data level is the same at the rise and fall of this noise, so "data start" is almost never set due to noise. Similarly, "end of data and latch to register" requires that the data be at H level at the rising edge of the clock and at L level at the falling edge of the clock, but since noise is an instantaneous pulse, , since the data level is the same at the rise and fall of this noise, "end of data and latch to register" is almost never set (the strobe is output to the register) due to noise; Even if erroneous data is shifted into the shift register, the data is almost never latched into the register.

In this way, since the data levels at the rising and falling edges of the clock are different, the operations of "start of data" and "end of data and latching into the register" are performed, thereby reducing noise. It becomes extremely difficult to be affected by

[0021]

As explained above, according to the present invention, the shift-in clock and strobe are generated based on the clock and data, so only two control lines, a clock line and a data line, are required. It became like this,
The number of control lines can be reduced. Furthermore, by setting the condition that the logic levels of data at the rising edge and falling edge of the clock are different, it is possible to obtain a circuit that is extremely resistant to the influence of noise.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an example of a latch circuit according to the present invention.

FIG. 2 is a circuit diagram of an example of a fall detection circuit of the same latch circuit.

FIG. 3 is a timing chart of the same latch circuit.

FIG. 4 is a configuration diagram of an example of a conventional latch circuit.

FIG. 5 is a timing chart of the same circuit.

FIG. 6 is a specific configuration diagram of an example of the circuit.

[Explanation of symbols]

1... Shift register, 2... Register, 3... Clock strobe generation circuit, 11... D-type flip-flop circuit,
12...Exclusive OR circuit, 13, 15, 23~
25, 27...AND circuit, 17...Fall detection circuit, 26
...S-R type flip-flop circuit.

Claims (2)

[Claims] 1. A latch circuit that inputs data in serial format in synchronization with a clock, stores the data in a buffer, and then latches it in a register, wherein data is input to the buffer based on the rising and falling edges of the clock and the data. A latch circuit characterized in that it is provided with means for generating a clock for data acquisition and a strobe for permitting transfer from a buffer to a register. 2. A strobe that generates a clock for taking in data into a buffer and a strobe that permits transfer from the buffer to a register on the condition that the logic levels of data at the rising and falling edges of the clock are different. 1. The latch circuit described in 1.