JPH0437219A - Clock generating circuit and information processor with the same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock generation circuit, and more particularly to a tarlock generation circuit for a semiconductor integrated circuit device built into an information processing device that performs logic operations based on a clock.

[Conventional technology]

In an information processing device that performs logic operations based on a clock, it is important to manage clock timing in order to prevent malfunctions of internal logic and increase speed.

In particular, when there are multiple information processing devices, in order to transfer data reliably and at high speed between the information processing devices, the clocks of each information processing device must be synchronized, and the phase between the clocks called clock skew must be adjusted. It is desirable that the fluctuations be small.

In order to meet such requirements, conventionally
As described in Japanese Patent No. 8020, a clock generation circuit that generates a clock synchronized with an external signal was used. Also, regarding this type of lock generation circuit, see IE Journal of Solid State, Circuit, Nisshi 22. Number 2 (1987
), pages 255 to 261 (IEEE Journal
al of 5olid-5tateCircuits
, VoR, SC22, Nn2 (1987) p p22
5-2'61), the phase-locked loop (hereinafter abbreviated as PLL: Phase-LockedL)
ooρ) is shown to be used.

FIG. 2 shows a block configuration of a conventional clock generation circuit using this PLL. The clock generation circuit 100 includes a phase comparator 10. Low pass filter (LPF) 20. Voltage controlled oscillator (VC○) 3o.

It is composed of a PLL consisting of a frequency divider 40. Here 1
The phase comparator 1o constantly compares the phase difference between the timing signal ST and the synchronized clock signal CP related to the external signal, and smoothes the output caused by this phase difference with the LPF 20, and outputs vC○.
30 control signals. vC○30 is LPF20
The oscillation frequency is increased/decreased according to the output of the oscillation frequency, and the oscillation frequency is increased/decreased in accordance with the output of the synchronous clock signal, which is then output as a synchronized clock signal via the branch divider 40.

In this clock generation circuit, when the phase of the timing signal is ahead of the phase of the in-phase clock signal, the 1 phase comparator 10 detects the phase difference, and the
○ Operates to increase the oscillation frequency of 3o. VCO3
If the oscillation frequency of 0 increases, the frequency of the synchronized clock signal increases, so the phase of the synchronized clock signal advances and operates to reduce the phase with the timing signal. Conversely, when the phase of the timing signal lags behind the phase of the synchronous clock signal, it operates to delay the phase of the synchronous clock signal, thereby similarly reducing the phase difference between the timing signal and the synchronous clock signal.

That is, the clock generation circuit 100 synchronizes the phase difference between the timing signal and the synchronized clock signal and operates so that the frequencies match, thereby fulfilling the role of automatic frequency control.

[Problem to be solved by the invention]

First, problems with the above-mentioned conventional technology will be explained.

In the clock generation circuit 100 shown in FIG.
The PLL feedback system consisting of the following realizes phase synchronization and frequency matching between the timing signal and the synchronous clock signal. However, the frequency range of the synchronous clock signal is
Since the oscillation frequency variable range is limited to 30, the gain of vCO must be increased to widen the frequency range. On the other hand, in order to reduce the tarot skew, the open loop gain of the PLL must be reduced by reducing the gain of the vCO or the wide area gain of the LPF.

In this way, expanding the frequency range of the synchronized clock signal and reducing tarot skew cannot be achieved simultaneously by increasing the vCO gain alone. Said IE Journal of
Solid state, circuit, varnish 22. In the clock generation circuit shown in No. 2 (1987), pages 255 to 261, the wide-range gain of the LPF is reduced to achieve both. Here, if the wide-range gain is made small, the time constant of the LPF becomes small and the PLL becomes unstable, so a 0.1 μF external capacitor is used to secure the time constant. As described above, when the capacitor is externally attached, there is a problem in that noise enters through the lead pin and increases the skew of the synchronized clock signal.

An object of the present invention is to provide a clock generation circuit that operates by following an externally input timing signal whose frequency changes over a wide range and generates a synchronous clock signal with a small lock skew.

[Means to solve the problem]

The above object has a phase comparison means, a loop filter means for smoothing the output of the phase comparison means, and a voltage controlled oscillation means for generating a frequency signal according to the output level of the loop filter means, and a timing signal inputted from the outside to the phase comparison means, and outputs a synchronized clock signal synchronized with the timing signal, wherein the output of the low-pass filter means is input and the voltage controlled oscillation is performed. This is achieved by providing free-running frequency control means that changes the free-running frequency of the means.

[Effect]

The PLL changes the output of the loop filter means higher when the frequency of the timing signal becomes higher than the synchronized clock signal. Further, the free-running frequency control means changes the center frequency of oscillation of the voltage controlled oscillation means to a higher side when the output of the loop filter means becomes higher. As a result, when the frequency of the timing signal becomes higher, the frequency range of the synchronous clock signal of the clock generation circuit is also changed to a higher frequency. Conversely, when the frequency of the timing signal becomes lower, the frequency range of the synchronous clock signal is changed to a lower frequency. In this way, the clock generation circuit having the free-running frequency control means can synchronize with timing signals of a wide range of frequencies because the frequency range of the synchronization clock signal is changed according to the frequency of the timing signal.

Furthermore, since the operating frequency range can be secured by the free-running frequency control means, the gain of vCO can be reduced to reduce the skew of the synchronous clock signal.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a block configuration of a first embodiment of the present invention. As shown in the figure, this embodiment is a tarlock generation circuit 100 using a PLL, and the same reference numerals as in the conventional example in FIG. 2 indicate parts having the same functions and configurations. In the figure, the difference from the conventional example in Figure 2 is that the loop filter output signal V
A free-running frequency control circuit 50 is provided which receives F as an input and changes the center frequency at which the VCO 30 oscillates according to the voltage.

This control circuit 50 has vCO3 at the output of LPF 2.0.
outputs a signal Io that changes the center frequency of the oscillation. The frequency of the timing signal ST is the synchronous clock signal C
When the value becomes higher than P, the PLL changes the output of the PF 20 to a higher value. Due to this change, the control circuit SO becomes
A signal 1o that changes the center frequency of the oscillation of the VCO 30 to a higher value is output. Conversely, when the frequency of the timing signal becomes lower, the center frequency of the VCO 30 is changed to a lower value.

This operation will be explained using the vCO characteristic diagram shown in FIG. This characteristic shows the relationship between the input voltage VF of vCO and the frequency of the output signal CP○. The frequency of the timing signal ST becomes higher than the synchronous clock signal CP, and the LPF20
When the output of changes to the higher side, the free-running frequency control signal I
O changes to IO, and the center frequency of vCO changes to a higher one. Conversely, when the frequency of the timing signal decreases,
The control signal Io changes to Io, changing the center frequency of vCO downward.

Here, the synchronous clock signal CP is a signal obtained by dividing the oscillation output signal CPO of the VCO 30 by a frequency divider 40. Therefore, the frequency range of the synchronous clock signal CP is
It is proportional to the oscillation frequency range.

In this way, according to this embodiment, the frequency range of the synchronization clock signal is changed according to the frequency of the timing signal ST, so that synchronization can be performed with a timing signal having a wide range of frequencies. Furthermore, since the operating frequency of the vCO is changed by the free-running frequency control circuit, the gain of the vCO can be reduced and the skew can be reduced. Therefore, according to this embodiment, the timing signal S
Operates in a wide frequency range that can accommodate frequency changes of T,
Moreover, a tarock generation circuit with small skew can be realized.

FIG. 4 shows a block diagram of another embodiment of the invention. 1st
Parts having the same functions and configurations as those of the conventional example shown in the figure are indicated by the same reference numerals. Here, the block configurations of the LPF 20, vCO 30, and free-running frequency control circuit 50 are shown in detail. For specific examples of each block, please refer to Part 5.
This will be described later with reference to FIGS.

In FIG. 4, the LPF 20 includes constant current circuits 21 and 22.
, capacitor 23, and MOS transistor 24.25
and resistors 26 to 28. Here, LPF20
The pulse widths of the outputs PU and PD of the phase comparator 10, which are the input signals of the timing signal ST and the synchronized clock signal CP, are
It changes depending on the phase difference of U. Since the constant current circuits 21 and 22 are switched by these pulse signals, a current proportional to the phase difference between ST and CP flows through the capacitor 23. As a result, the voltage VFC of the capacitor 23 is
This is a signal obtained by integrating the phase difference between and CP.

Furthermore, since the MoS transistors 24 and 25 are also switched by the pulse signals ST and CP, the resistors 26 to 28
The divided voltage VFR changes with a pulse width equal to that of the PU and PD, and its average voltage is proportional to the phase difference between the ST and CP. In this way, the LPF 20 outputs the voltage VFR proportional to the phase difference and the voltage VFC integrated with the phase difference.

VC030 is V/I31. Addition circuit 33. Consists of a current controlled oscillator (CCO) 32, output voltage VF of LPF 20
The voltage difference between C and VFR is converted into a current by V/I31.

The CCO 32 receives this current and the control current I of the control circuit 50.
A signal cpo with a frequency proportional to the sum of O is output.

The free-running frequency control circuit 50 is a voltage-current conversion circuit (V/I
) 51, 52 and a capacitor 53. Here, the V/I 51 operates to convert the difference between the input voltage VFR and the reference voltage VRF inside the V/I into a current, and this current is integrated by the capacitor 53. As a result, the voltage of the capacitor 53 is such that the output voltage VFC of the LPF 20 is equal to the reference voltage V
It becomes stable at the point where P and F are equal. The V/I 52 converts this voltage into a free running frequency control current Io of vCO and outputs it.

FIG. 5 shows an embodiment of the phase comparator 10. This circuit is
Inverter 101 and 102, 112 and 113.2 manual power N
AND103~108.3 human power NAND110 and 111
．． This is a frequency/phase comparison type phase comparator consisting of a four-power NAND109 gate circuit. These circuits convert the phase difference between the rising edges of the timing signal ST and the synchronous clock signal CP into pulse signals PU and PD, and output the pulse signals PU and PD.

This operation will be explained using the timing chart shown in FIG. When the phase of the timing signal ST is ahead of the phase of the synchronized clock signal, the signal P is shifted as shown in (A) in the figure.
A pulse signal with a pulse width corresponding to the phase difference is output to U. On the other hand, when there is a delay, a signal corresponding to the phase difference is output as the signal PD, as shown in (B) in the figure. A synchronous state occurs when the rising edge of the synchronous clock signal CP matches the phase of the timing signal ST, and there is no change in any of the outputs, as shown by (C) in the figure.

That is, in this embodiment, the phase difference between the timing signal ST and the synchronous clock signal CP is converted into pulse widths of PU and PD and output.

FIG. 7 shows an embodiment of the loop filter 20.

In this embodiment, inverter gate circuits 201, 202゜21
2.206 and MOS transistor 204°205.2
07,208,210,213,214°221~22
4, resistors 203, 215 to 216, and capacitor 211
It consists of Here, the MOS transistor 204,
205, 210, and 207° and 208 constitute current mirror circuits, respectively.

A constant current determined by a resistor 203 is supplied to a current switch constituted by MOS transistors 211 to 224. This current switch is connected to the output signal PU of the phase comparator 10.
, PD, and are driven differentially by signals inverted by inverter gates 201 and 202. Therefore, the MOS transistors 208 and 2 which are the output of the current mirror
There is no change in the drain current of 10, and high-speed current switching is possible. In addition, the input/output connected input/output gate 206 is a dummy switch MOS transistor 221.
This circuit applies a bias to the drains of the differential MOS switches 211 to 214, so that the parasitic capacitance charge share is small and current switching can be performed with high precision. In this way, since a current switched at high speed and with high precision can be passed through the capacitor, the output voltage VFC becomes an accurate integral value of the input phase.

On the other hand, MOS)-transistor 213. Resistance 215-21
7. The inverter gate 212 operates with the output signals PU and PD of the phase comparator 10, and its output VFR is set to
and 217, and when either PU or PD becomes '1'', the MOS transistor 213 or 21
4 becomes ON state, and the output voltage VFR changes to positive or negative by ΔV. Since this changing time is equal to the pulse width of the PU and PD, the average value of this changing voltage is proportional to the input phase difference of the tarock generating circuit 10.

Through the above-described operation, the timing 20 of this embodiment generates the voltage VFR proportional to the input phase and the voltage VFC proportional to the integral value of the input phase.

FIG. 8 shows an embodiment of the voltage controlled oscillator 30.

This embodiment is a MOS)-transistor 302~310°31
4.316, 319, 322, bipolar transistor 311, 312, 317, 318, diode 313,
315, resistance 301. Capacitor 325, inverter 3
It consists of 23 parts. Here, transistors 302 to 3
07 and resistor 301 convert the voltage difference between input voltage VFC and VFR into current Ii, and MOS)-transistor 305
and is output from the drain of 307. Furthermore, the MO3I transistors 308 to 309, 314, 316, bipolar transistors 311, 312, 317, 318, diodes 313, 315, and capacitor 325 constitute a current controlled oscillation circuit, and this oscillation frequency is the same as that of the MO3I transistor 308. Can be controlled by drain current. This oscillation frequency fo is determined by setting the capacitance of the capacitor 325 as Co, the forward voltage of the diodes 313 and 315 as Vaε, and the MOS
) - Assuming that the sizes of the transistors 308 to 310 are equal, the following formula % formula
This is a circuit that converts the signal to a CMOS level signal of ~VDD. As shown in equation (1), the voltage controlled oscillation circuit of this embodiment can change the center of the oscillation frequency using the control current Io from the free-running frequency control circuit.

FIG. 9 shows one embodiment of the frequency divider 40. In this embodiment, the clocked inverter gate circuit 402°404.412
, 414 and inverter gate circuits 403, . The feedback type latch circuit 4o1゜411 by 413 is fed back via the inverter gate circuit 405, and each feedback type latch circuit is
The Q output signals CPo and CPO are configured to be driven by signals via an inverter gate circuit 406.

With this configuration, the frequency of CPO, which is the output signal of vC○, is divided into 1/2 and output as the synchronous clock signal CP.

FIG. 10 shows an embodiment of the free-running frequency control circuit 50.

In this embodiment, MOS transistors 502 to 508.511
514, resistors 509 and 510, and a capacitor 515. Here, MOS transistors 502 to 508
, 511, resistor 509, and 511 are voltage-current conversion circuits that convert input voltage VFC into current. This circuit consists of resistor 5
Voltage V REF divided by 09 and 510 and input voltage VF
The differential voltage of C is converted into a current and passed through the capacitor 511. This current output changes between positive and negative, and the output point needs to have a wide voltage change range. For this reason, a constant current current mirror circuit made up of PMOS transistors 502 to 504 and a current mirror circuit that changes depending on the input voltage made up of NMOS transistors 507 and 511 are provided, and the current mirror outputs of these are connected.

The voltage of the capacitor 511 is converted into a current by a MOS transistor 514, and this current is converted to a current by a MOS transistor 512,
The control current I is converted by a current mirror composed of 513
o is output.

FIG. 11 shows an embodiment of an information processing apparatus constructed using the clock generation circuit shown in FIG. 1 or 2. In FIG. Information processing LSIs 710 to 730 are clock generation circuits 711 to 71
It has 3 built-in. Each clock circuit is controlled by a common timing signal output from a timing control circuit 60. Therefore, the clock signals that control the logic blocks 712, 713, 722, 723, and 732 of each LSI 710 to 730 are all synchronized, and data transfer between LSIs via the local bus 750 and system bus 760 is synchronized. It can be done reliably.

Furthermore, since data transfer can be performed reliably, high-speed data transfer is possible, and a high-speed information processing device can be realized.

〔Effect of the invention〕

As explained above, according to the present invention, the free-running frequency control means operates so that the oscillation frequency range of the voltage-controlled oscillation means changes with the output level of the loop filter means, so that the frequency of the timing signal changes. Also, the frequency range of the synchronized clock signal can be synchronized to the frequency of the timing signal. Further, since the gain of the voltage controlled oscillation means can be set in the timing signal regardless of frequency changes, it is possible to lower the gain of the voltage controlled oscillation means and reduce clock skew.

This makes it possible to reliably synchronize data processing operations including data transfer between multiple information processing devices.

[Brief explanation of the drawing]

FIG. 1 shows a clock generating circuit according to an embodiment of the present invention, FIG. 2 shows a conventional clock generating circuit, FIG. 3 shows characteristics of a voltage controlled oscillator according to the present invention, and FIG. 4 shows another embodiment of the present invention. 5 is a block diagram of an embodiment of the phase comparator 10, FIG. 6 is a time chart of the phase comparator 10 shown in FIG. 5, and FIG.
8 is a configuration diagram of an embodiment of the voltage controlled oscillator 30, FIG. 9 is a configuration diagram of an embodiment of the frequency divider 40, and FIG. 10 is a configuration diagram of an embodiment of the frequency divider 40. FIG. 11, which is a block diagram of one embodiment of the running frequency control circuit 50, is an information processing device using the clock generation circuit of the present invention. 10 Phase comparator, 20... Loop filter, 30 Voltage controlled oscillator, 40 Frequency divider, 50 Free running cycle Figure 2 Figure 3 Input gray Zb diagram (^) (Bn (C)

Claims (1)

[Claims] 1. Phase comparison means for outputting a signal according to the phase difference between two input signals, loop filter means for inputting the output signal of the phase comparison means and controlling transfer characteristics, and the loop filter. voltage-controlled oscillation means for generating a signal with a frequency corresponding to the output signal of the oscillation means, outputting a clock signal based on the output signal of the oscillation means, and combining the clock signal with a timing signal given from the outside; is input to the phase comparison means, the clock generation circuit is characterized in that it is provided with free-running frequency control means that receives the output signal of the loop filter means and controls the free-running oscillation frequency of the voltage-controlled oscillation means. Clock generation circuit. 2. A phase comparison means for outputting a signal according to the phase difference between two input signals, a loop filter means for inputting the output signal of the phase comparison means and controlling the transfer characteristic, and a loop filter means for controlling the transfer characteristic according to the output signal of the loop filter means. a voltage-controlled oscillation means for generating a signal with a frequency of a given frequency; and a distribution means for distributing a clock signal based on an output signal of the oscillation means into a plurality of clock signals;
Free-running frequency control means receives the output signal of the loop filter means and controls the free-running oscillation frequency of the voltage-controlled oscillation means, and includes a clock signal output from the distribution means and a timing signal given from the outside. a clock generation circuit, which inputs the phase comparison means to the phase comparison means. 3. In claim 1 or 2, the free-running frequency control means includes an integrating means for integrating the output signal of the loop filter means, and an output of the integrating means for integrating the output signal of the voltage-controlled oscillation means. A clock generation circuit comprising signal conversion means for converting an oscillation frequency into a control signal. 4. In claim 1 or 2, the loop filter means is constituted by a delay element means whose transfer characteristic is a first-order lag and a proportional element means whose transfer characteristic is constant with respect to frequency change, and the delay circuit A clock generation circuit characterized in that an output of the means is used as an input of the free-running frequency control means. 5. A plurality of information processing devices are connected via a bus, and each information processing device has a clock generation means that generates a clock signal synchronized with a commonly given timing signal, and generates other information based on the clock signal. In an information processing system that synchronizes and executes processes including data transfer between processes, the clock generation means provided in each of the information processing apparatuses includes a phase comparison means for outputting a signal according to a phase difference between two input signals. a loop filter means for inputting the output signal of the phase comparison means to control the transfer characteristic; a voltage controlled oscillation means for generating a signal having a frequency corresponding to the output signal of the loop filter means; It has a free-running frequency control means for controlling a free-running oscillation frequency, and is configured by inputting a clock signal output from the voltage-controlled oscillation means and a clock signal given from the outside to the phase comparison means. information processing system.