JPH04373334A - Multiplexer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applicable to, for example, a time division multiplex PC.
The present invention relates to a multiplex conversion device that performs time slot replacement in time division multiplex data transmission such as M communication.

0002

2. Description of the Related Art When exchanging time slots between n pieces of multiplexed data, generally the n pieces of multiplexed data are multiplexed onto one highway. After the order of each time slot on the highway is changed using a time switch, the time slots are changed by separating the highway into n pieces of multiplexed data. Here, the data on the highway is a multiplex of n pieces of multiplexed data, so it is very fast, and the time switch is required to operate at high speed.

Now, in the case of PCM communication, one time slot has 8 bits. Therefore, after converting each of the n pieces of multiplexed data into 8-bit parallel data, the 8-bit parallel data obtained by bit-multiplexing the n pieces of multiplexed data, each of which has been made into 8-bit parallel data in this way. If input into the time switch, the speed of the data input into the time switch is 1/1 compared to the above case.
8, and the operating speed of the time switch can be reduced.

However, in this case, if the number n of multiplexed data to be handled exceeds the data amount of one time slot, it is not possible to bit-multiplex the n multiplexed data as parallel data. Therefore, one time switch can only handle up to n pieces of multiplexed data, that is, up to 8 pieces of multiplexed data in the case of PCM communication. n or more, that is, PCM
In the case of communication, when exchanging time slots between eight or more multiplexed data, two or more time switches,
A switch network with a so-called T-S-T structure must be constructed, in which a space switch and two or more time switches are connected in stages.

[0005]

[Problems to be Solved by the Invention] As described above, in the conventional multiplex conversion device, when parallel data is input to the time switch in order to reduce the operating speed of the time switch, it is handled by one time switch. The number of multiplexed data that can be created is limited to less than the amount of data (number of bits) of one time slot. Therefore, when exchanging time slots between multiplexed data with more than the number of bits in one time slot, a switch circuit network with a T-S-T structure must be configured, which causes the problem of increased circuit scale. arise.

The present invention has been made in consideration of the above circumstances, and its purpose is to reduce the amount of data in one time slot without increasing the operating speed of the time switch or increasing the number of switch circuits. An object of the present invention is to provide a multiplex conversion device that can efficiently exchange time slots between multiplexed data exceeding the amount (number of bits).

[0007]

[Means for Solving the Problems] The present invention provides speed converting means provided for each of n pieces of multiplexed data and converting the speed of the corresponding multiplexed data into n bits per time slot; serial-to-parallel converting means provided corresponding to each of the multiplexed data and converting the multiplexed data subjected to speed conversion by the speed converting means into first n-bit parallel data, the serial-to-parallel converting means The n pieces of first n-bit parallel data obtained by each means are made into second n-bit parallel data obtained by time-division multiplexing the same bits of each first n-bit parallel data in one time slot period. The second n-bit parallel data is used for the time slot replacement.

[0008]

[Operation] By taking such measures, each multiplexed data is speed-converted to n bits per time slot, and then converted to n-bit parallel data. Thereafter, each parallel data is made into n-bit parallel data obtained by time-division multiplexing the bits of the same order in one time slot period, and is used for time slot replacement. Therefore, even if the number n of multiplexed data is larger than the number of bits per time slot of multiplexed data, n pieces of multiplexed data are 1
The data is multiplexed into two parallel data and used for time slot replacement.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the main part configuration of a multiplex conversion apparatus according to this embodiment. Here, an example is shown in which time slots are exchanged between n (9 or more) pieces of PCM multiplexed data PCM-#1 to PCM-#n, each time slot consisting of 8 bits.

In the figure, 1-1 to 1-n are speed converters;
2-1 to 2-n are serial-to-parallel conversion units, which are provided corresponding to the PCM multiplexed data PCM-#1 to PCM-#n, respectively. Reference numeral 3 denotes a multiplexing section, into which the respective output signals of the serial-parallel converting sections 2-1 to 2-n are input. 4 is a time switch to which the output signal of the multiplexer 3 is input.

Next, the operation of the multiplex converter configured as described above will be explained. First, in the speed conversion section 1-1, the PC
It receives M multiplex data PCM-#1 and converts the speed of this PCM multiplex data PCM-#1 from 8 bits per time slot to n bits per time slot. In FIG. 2, S1 indicates the state of the PCM multiplexed data input to the speed converter 1-1, and S2 indicates the state of the PCM multiplexed data output from the speed converter 1-1.

The PCM multiplex data whose speed has been converted into n bits per time slot by the speed converter 1-1 is input to the serial-parallel converter 2-1. Serial-parallel converter 2
-1 is the P whose speed has been converted by the speed converter 1-1.
CM multiplexed data PCM-#1 (serial data) is converted into n-bit parallel data (hereinafter referred to as first parallel data) as shown by S3 in FIG. At this time, the serial-parallel converter 2-1 adds sub information SD-#1 to the surplus bits generated by converting the speed of PCM multiplexed data from 8 bits per time slot to n bits per time slot. do. Side information SD-#
1 is parity information, signaling, ST (status) bit, etc. for each channel, and is given together with PCM multiplex data PCM-#1.

[0013] In the above, PCM multiplex data PCM-#
1, but PCM-#2 to PCM-#
Similar processing is performed for speed converters 1-2 to 1-n and serial-parallel converters 2-2 to 2-n for speed converters 2-2 to 2-n. That is, n signals in the state shown in S3 are input to the multiplexing unit 3.

The multiplexer 3 includes serial-parallel converters 2-1 to 2-1.
The n pieces of first parallel data output from each of 2-n are bit-multiplexed into one piece of n-bit parallel data (hereinafter referred to as second parallel data) as shown by S4 in FIG. . That is, the signals of the same order of each first parallel data are multiplexed into one signal. Therefore,
The first-order signal of the second parallel data S4 is data of the first bits of the PCM multiplexed data PCM-#1 to PCM-#n arranged serially within one time slot period. The second highest signal is PCM multiplexed data PCM-
The second bit data of #1 to PCM-#n are serially arranged within one time slot period. and the nth
The PCM multiplexed data PCM-#1 to PCM-
The data of the n-th bit of #n is serially arranged within one time slot period.

[0015] In the second parallel data as described above, the upper eight signals are PCM multiplexed data PCM-#1 to PC
M-#n multiplexed signal, the next m signals are sub information S
The signal obtained by multiplexing D-#1 to SD-#n and the lower [n-8-m] signals are unused signals. Of the second parallel data output from the multiplexer 3, only the upper 8+m bits out of the n bits are sent to the time switch 4.
The time slots are replaced by the time switch 4 according to a well-known procedure. Note that the lower [n-8
-m] bit is not necessary for time slot replacement, so it is not given to the time switch 4 and is discarded as is.

Thus, according to this embodiment, n pieces of PCM multiplexed data of 8 bits per time slot are
Since n-bit parallel data is multiplexed per time slot and given to the time switch 4, the number n of PCM multiplexed data to be processed is equal to 1 of the PCM multiplexed data.
Even if the number of bits per time slot exceeds "8", time slot replacement can be performed with one time switch 4. Therefore, there is no need for a switch circuit network having a T-S-T structure, and there is no increase in the configuration.

The operating speed of the time switch 4 is [(n-8)/8 of the clock frequency of the original PCM multiplexed data.
] times the operating speed (n times the clock frequency of the original PCM multiplex data) when n pieces of PCM multiplex data are simply multiplexed onto one highway.

Furthermore, in this embodiment, since the sub information is inserted into the surplus bits generated when the number of bits per time slot is converted to n bits, the system for replacing the time slots of the sub information is It is not necessary and the configuration can be simplified, and it can be processed together with the main data in the PCM multiplexed data, resulting in simplification of processing.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the sub information is inserted into the surplus bits, but the sub information may be processed in a separate system as in the past. Further, in the above embodiment, the processing target is described as PCM multiplexed data, but the processing target is not limited to PCM multiplexed data. In addition, various modifications can be made without departing from the gist of the present invention.

[0020]

According to the present invention, speed converting means is provided corresponding to each of the n pieces of multiplexed data and converts the speed of the corresponding multiplexed data into n bits per time slot; serial-to-parallel converting means provided corresponding to each of the multiplexed data and converting the multiplexed data subjected to speed conversion by the speed converting means into first n-bit parallel data; The n pieces of first n-bit parallel data obtained in each case are made into second n-bit parallel data obtained by time-division multiplexing the same bits of each first n-bit parallel data in one time slot period. Since the n-bit parallel data of 1 time slot is used for the above-mentioned time slot replacement, it is possible to transfer between multiplexed data of more than the data amount (number of bits) of 1 time slot without increasing the operating speed of the time switch or increasing the switch circuit network. This provides a multiplex conversion device that can efficiently exchange time slots.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main part configuration of a multiplex conversion device according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing signal states of each part in FIG. 1;

[Explanation of symbols]

1-1 to 1-n...speed conversion section, 2-1 to 2-n...
Serial-parallel converter, 3...multiplexer, 4...time switch.

Claims (1)

[Claims] 1. A multiplex conversion device that switches time slots between n pieces of multiplexed data (n is an integer of 2 or more) each of which is time-division multiplexed with data of a plurality of channels, wherein each of the n pieces of multiplexed data is a speed conversion means provided corresponding to each of the n pieces of multiplexed data and converting the speed of the corresponding multiplexed data into n bits per time slot; serial-to-parallel converting means for converting the multiplexed data into first n-bit parallel data; and n first n-bit parallel data obtained by each of the serial-to-parallel converting means. The same bits of the n-bit parallel data are time-division multiplexed in one time slot period to generate second n-bit parallel data, and the second n-bit parallel data is provided for the time slot replacement. Characteristic multiple conversion device.