JPH0437447B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a bidirectional bus buffer inserted in a bus line.

[Technical background of the invention and its problems]

An example of a conventional bidirectional bus buffer is shown in the first example.
As shown in the figure. This bidirectional bus buffer is inserted between bus lines 1 and 2, and 3 and 4 are connected to control signals φ ₁ ,
A clocked inverter operated by _φ2 , 5,
6 is an inverter. The clocked inverter 3 and the inverter 5 are connected in cascade in the path _P1 direction.
The clocked inverter 4 and inverter 6 are the path
P Connected in cascade in _two directions. 7 and 8 are terminals, which are connected to bus lines 1 and 2, and control signals φ ₁ and φ ₂ are applied depending on the usage direction and interruption status of the bus lines, and paths P ₁ and P ₂ are formed. or blocked.

However, in the conventional circuit type described above, the inverters 5 and 6 are operated from the selected path side even if the inverters are not selected, and in the case of a CMOS circuit configuration, there is a problem that power consumption increases. An example of an improved circuit is shown in FIG. 2.
The difference from FIG. 1 is that two-input NAND gates 9 and 10 are used instead of inverters 5 and 6, and control signals φ ₁ and φ ₂ are applied, respectively. By providing the gates 9 and 10 in this way, the route P ₁ or P ₂ that is blocked can be blocked by the gate 9 or 1.
The output of 0 is always kept at a high level, and the above problem of FIG. 1 is solved.

However, gate inputs of a plurality of systems are usually connected to the bus line. When no signal is present on the bus line, in the circuit shown in FIG. 2, both bus lines 1 and 2 are in an open state, and potential fluctuations can easily occur. As a result, the gate inputs of the plurality of systems described above fluctuate, and the resulting through current between the power supplies increases the power consumption of the system. Therefore, it is desirable that the bus lines 1 and 2 be held at a high level or a low level when not in use. Therefore, conventionally, as shown in Fig. 3, a bidirectional bus buffer 11
At the same time, holding circuits 12 and 13 called bus terminators were also used, but this configuration required two sets of bus terminators for each bidirectional bus buffer 11, which caused trouble in the system configuration.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a bidirectional bus buffer that can reduce power consumption without requiring a conventional bus terminator.

[Summary of the invention]

In order to achieve the above object, the present invention provides a logic gate provided in a bus buffer path with a data retention function, so that the bus line can be fixed at a high level or a low level when the bus line is not in use. This is what I did.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 4, the output of the logic gate 21 is
Connect the output of the logic gate 23 to the input of the state output buffer 22 and connect the output of the logic gate 23 to the 3-state output buffer 24.
Connect to the input of 3-state output buffer 24
The output of the logic gate 21 and the input of the logic gate 21 are connected to the bus line 1.
The output of the three-state output buffer 22 and the input of the logic gate 23 are connected to the connection terminal 26 of the bus line 2. logic gate 2
The input and output terminals of a positive feedback logic gate 27 are connected between the input and output terminals of the logic gate 23, and the input and output terminals of a positive feedback logic gate 28 are connected between the input and output terminals of the logic gate 23.

FIG. 5 is a specific example of FIG. 4, in which the logic gates 21 and 23 are realized by inverters 21 ₁ 23 ₁ , and 3
State output buffers 22 and 24 are realized by clocked inverters 22 ₁ and 24 ₁ , and positive feedback logic gates 27 and 28 are realized by inverters 27 _{1 and} 28 ₁ .

Bus input logic gates 21 ₁ , 23 ₁ as above
By providing positive feedback logic gates 27 ₁ and 28 ₁ in , a data retention function is created. Therefore, when the bus lines 1 and 2 are not in use, the bus lines can be held at a high level or a low level, making it possible to reduce power consumption.

Depending on the system configuration, it may be sufficient to use only one path of the positive feedback gate. An example of its application is shown in FIG.

FIG. 7 shows a clocked inverter 28 ₂ , which controls the positive feedback logic gate with control signals φ ₁ and φ ₂ .
This is an application example realized with 27 ₂ , (inverted pulses of ₁ , ₂ , φ ₁ , φ ₂ ). Here, when the output of clocked inverter ₂₂₁ is floating, the level of bus line 2 is fixed by the output of clocked inverter ₂₈₂ . On the other hand, when the output of clocked inverter ₂₄₁ is floating, the level of bus line 1 is fixed by the output of clocked inverter ₂₇₂ .

Figure 8 shows NAND gate 2 in the bus input logic gate.
1 ₂ , 23 ₂ and convert them into clock pulses φ ₁ , φ ₂
This is an example of an application controlled by Needless to say, the present invention also applies to implementations using other gates. In FIG. 8, a NAND gate ₂₁₂ prevents floating of the clocked inverter ₂₂₁ when the pulse _φ1 is at a low level, and this gate 21a
Eliminate floating of bus line 1 with high level output. On the other hand, when the pulse φ ₂ is at a low level, the floating of the clocked inverter 24 ₁ is prevented by the NAND gate 23 ₂ , and the floating of the bus line 2 is eliminated by the high level output of this gate 23 ₂ .

The present invention relates to the circuit configuration of the input and output portions of a bidirectional bus buffer, and therefore, circuits 31, 32, etc. having other functions are configured between the input and output circuits as shown in FIG. The invention also falls under the present invention.

In the above embodiment, the illustrated clocked inverter is used as the logic gate that is opened and closed by the control signals φ ₁ and φ ₂ , but the same applies to the case where it is realized by a combination of other logic gates, which falls under the present invention. do. FIG. 10 shows an embodiment using a clocked inverter using transmission gates 22 ₂ and 24 ₂ and inverters 22 ₃ and 24 ₃ .

According to the above embodiment, the following advantages are provided. In other words, in the past, the system configuration included a bus terminator IC for each bidirectional bus buffer ICI as shown in Figure 3.
However, the present invention eliminates the need for two bus terminator ICs, simplifying the system configuration. Furthermore, since the present invention has a data hold function, the level of the bus line is fixed, eliminating the through current of the CMOS gate of the system due to fluctuations in the bus line due to noise, etc.
Low power consumption can be achieved. In addition, although this circuit is intended to be used as a bidirectional bus/buffer IC for system configuration, it can also be applied to circuits inside the IC.
In this case, if the configuration shown in FIG. 5 is adopted compared to the prior art shown in FIG. 3, the number of inverters is reduced by two, so the number of elements is reduced by four per bus line.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a bidirectional bus buffer having advantages such as a simplified configuration and low power consumption.

[Brief explanation of drawings]

Figure 1 is a conventional bidirectional bus buffer circuit diagram, and Figure 2 is an improved bidirectional bus buffer circuit diagram.
3 is a bidirectional bus buffer circuit diagram showing another conventional example; FIG. 4 is a configuration diagram showing an embodiment of the present invention; FIG. 5 is a specific circuit diagram of the same configuration; 6 to 10 are circuit diagrams showing other embodiments of the present invention. 1, 2... Bus line, 21, 23... Logic gate, 22, 24... 3-state output buffer,
27, 28...Positive feedback logic gate.

Claims (1)

[Claims] 1 connect the output of the first logic gate to the input of the first 3-state output buffer, connect the output of the second logic gate to the input of the second 3-state output buffer, and connect the output of the second logic gate to the input of the second 3-state output buffer; The output of the buffer and the input of the first logic gate are connected at a first connection end, and the output of the first three-state output buffer and the input of the second logic gate are connected at a second connection end. A positive feedback logic gate is connected such that positive feedback is applied from the gate output to the gate input in at least one of the first and second logic gates, and at least one of the first and second connection ends is connected. A bidirectional bus buffer, characterized in that one potential is fixed at a positive feedback potential by the positive feedback logic gate.