JPH0437671B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for generating a pulse width modulated wave for reducing harmonics, that is, a pulse width modulated wave capable of reducing harmonic components in the same manner as a staircase wave.

It is already known that harmonic components can be reduced by pulse width modulating the output of an inverter that converts direct current to alternating current, instead of making it a simple rectangular wave, and making the output an array of multiple pulses. but,
The configuration of a conventional pulse width modulated wave generation circuit for controlling switching elements of an inverter is complicated, and the cost is inevitably high.

Therefore, the object of the present invention is to
An object of the present invention is to provide a circuit that can generate a pulse width modulated wave for driving an AC switching device so as to reduce harmonics with a relatively simple configuration.

To achieve the above object, the present invention will be described with reference to the reference numerals in the drawings showing the embodiments.
first, second, third, fourth, fifth and sixth switching elements for controlling the fourth, fifth and sixth switching elements;
This is a pulse width modulated wave generation circuit that generates a control signal of 1/2, which includes an oscillation circuit 10 that generates pulses with a duty ratio of 50% at a predetermined period, and an output of the oscillation circuit 10 of 1/M (where M is positive). a six-stage frequency divider 13 that divides the frequency into an integer (an integer); and a six-stage frequency divider 13 coupled to the output of the frequency divider 13 and having first, second, third, fourth, fifth, and sixth ring counter output terminals. a ring counter 14 and a first exclusive OR gate 16 connected to the first and second ring counter output terminals;
, a second exclusive OR gate 17 connected to the third and fourth ring counter output terminals, and a third exclusive OR gate 18 connected to the fifth and sixth ring counter output terminals. , a first ADN gate 19 connected to the oscillation circuit 10 and the first exclusive OR gate 16, and a second ADN gate 19 connected to the oscillation circuit 10 and the second exclusive OR gate 17. a third AND gate 21 connected to the oscillation circuit 10 and the third exclusive OR gate 18;
a fourth exclusive OR gate 22 connected to the AND gate 19 and the second ring counter output terminal;
a fifth exclusive OR gate 23 connected to the ring counter output terminal of the third AND gate 2;
1 and the sixth exclusive OR gate 24 connected to the sixth ring counter output terminal, and the first switching element 29 using the output of the fourth exclusive OR gate 22 as the first control signal. and said fourth exclusive OR gate 2
2 and the second switching element 30 for obtaining the fourth control signal.
NOT circuit 25 and the fifth exclusive OR gate 2
means for providing the output of No. 3 as the third control signal to the third switching element 31; and the means connected between the fifth exclusive OR gate and the fourth switching element 32; a second NOT circuit 26 for obtaining a fourth control signal;
means for applying the output of the sixth exclusive OR gate 24 to the fifth switching element 33 as the fifth control signal;
OR gate 24 and the sixth switching element 3
The present invention relates to a pulse width modulated wave generating circuit characterized in that it comprises a third NOT circuit connected between 4 and 27 for obtaining the sixth control signal, and 27.

According to the above invention, the oscillation circuit 10 and the frequency divider 1
3, ring counter 14, and nine gates 16
24 and three NOT circuits, that is, phase inversion inverters 25, 26, and 27. A sixth control signal can be formed. Also, frequency divider 1
By changing the frequency division ratio of 3, the number of pulses of the pulse width modulated wave can be easily changed.

Next, an inverter and a pulse width modulated wave generation circuit according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3.

In Fig. 1, 10 is an oscillation circuit that generates pulses with a duty ratio of 50% at a constant cycle as shown in Fig. 2A.
(where N is a positive integer).

1/M with the output of the oscillation circuit 10 as input (however,
The frequency divider 13 (in this embodiment, for convenience of explanation, M=2) is a frequency divider of a variable division ratio type for determining the number of pulses of the pulse width modulated wave. A frequency-divided output as shown in Figure B is generated.
Since the number of pulses of the modulated wave changes as the frequency division ratio 1/M of this frequency divider 13 changes, this can also be called a pulse number selection circuit.

A ring counter 14 of L stages (in this embodiment, for convenience of explanation, there are six stages) coupled to the output of the frequency divider 13 receives the output of the frequency divider 13 as an input.
The outputs shown in FIG. 2 C, D, E, F, G, and H are sent out from output terminals 1, 2, 3, 4, 5, and 6 in 6 stages.

15 is a pulse forming logic circuit which inputs the outputs of the first stage and second stage of the ring counter 14 and outputs the second pulse forming logic circuit.
First exclusive OR gate 1 producing the output of Figure 1
6. A second exclusive OR gate 17, 5 which receives the outputs of the third and fourth stages as input and generates the output shown in FIG. 2J.
It includes a third exclusive OR gate 18 which receives the outputs of stages 6 and 6 and generates the output of FIG. 2K. The pulse forming logic circuit 15 also includes first, second, and third exclusive OR gates 16, 17, 1
The circuit includes first, second, and third AND gates 19, 20, and 21 which receive the output of 8 and the output of the oscillation circuit 10, respectively, and generate the outputs L, M, and N in FIG. Furthermore, this logic circuit 15 includes the outputs of the first, second, and third AND gates 19, 20, and 21, and the even-numbered stages of the ring counter 14, such as 2 stages, 4 stages,
Figure 2 O, P, Q with the outputs of the 6 stages as inputs, respectively.
fourth, fifth and sixth exclusive generating outputs of
It includes OR gates 22, 23, and 24.

To explain this circuit in more detail, from the output terminal of the L stage of the L stage ring counter 14, the pulses of C to H in FIG. occurs. And, Figure 2 C~
Using one of the six rectangular waves of H as a reference rectangular wave, the reference rectangular wave C and a rectangular wave D delayed by 1/2L×2π are input to the exclusive OR gate 16, and the reference rectangular wave C A rectangular wave E that is delayed by 1/L×2π and a rectangular wave F that is delayed by 1/2L×2π are input to the exclusive OR gate 17, and a rectangular wave that is delayed by 2/L×2π from the reference rectangular wave C is input to the exclusive OR gate 17. The wave G and the rectangular wave H delayed by 1/2L×2π are input to the exclusive OR gate 18. As a result, pulses having a width of 1/2L×2π shown in FIG. Exclusive OR gates 16, 17, 18
By inputting the output of 1 and the output of the pulse generating circuit 10 to AND gates 19, 20, and 21, pulses with a duty ratio of 50% as shown in FIG. 2 L, M, and N are formed. That is, the pulses in FIG. 2A are the same as those in FIG.
A pulse that has passed only for a period determined by is obtained. After that, each exclusive OR gate 22, 23,
By inputting L, M, N in FIG. 2 and D, F, H in FIG. 2 to 24, pulse width modulated waves shown in O, P, Q in FIG. 2 are obtained. That is, in this example, M
= 2, L = 6, so 0 to π/12 (0 to 15°) and 11/12π to π (165° to 180°) in one period (2π)
,
π ~ 13/12π (180° ~ 195°), 23/12π ~ 2π (345° ~
360°), a pulse having a width of π/2L/M=π/24 and a duty ratio of 50% can be obtained. Also,
A pulse with a width of π-π/L=140° is obtained at π/12 to 11/12π (15° to 165°). Furthermore, with a phase difference of π/3 (60°) based on the first phase modulated wave shown in Figure 2 O, the second and third phase modulated waves are shown in Figure 2 P,
This occurs as shown in Q. Also, as is clear from Figure 3, by changing M, the number of pulses changes, -π/2L ~ +π/2π and π-π/2L ~ π+π/2L.
A number of pulses equal to M can be obtained in the period of . Therefore, the 1/M frequency divider 13 can be called a pulse number selection circuit.

The modulated waves O, P, and Q in FIG. 2 obtained from the logic circuit 15 are transmitted through the transistor 2 of the bridge type inverter.
9, 31, and 33, and the modulated waves R, S, and T in FIG. . Therefore, voltages U, V, and W in FIG. 2 are obtained between the output lines 35, 36, and 37.

Furthermore, between the output frequency f of the oscillator 11 and the output frequency f _OUT of the bridge type inverter, f _OUT = f
A relationship of ×1/N×1/M×1/2L is established. Therefore, by adjusting the frequency division ratio of the 1/N frequency divider 12, it is possible to keep the output frequency f _OUT constant even if M and L are changed.

As is clear from the above, according to this embodiment, it is possible to obtain a pulse width modulated wave for harmonic reduction that has an effect equivalent to that of a staircase wave with an extremely simple circuit configuration. Further, by configuring the frequency divider 13 and the ring counter 14 to be variable, it becomes possible to easily form various pulse width modulated waves.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto and can be further modified. For example, the gates constituting the logic circuit 15 may be constructed using various other gates that function equivalently to those shown in FIG. In addition, in order to perform voltage control, a signal is formed in which the modulated waves shown in FIG.
34 bases may be supplied. Alternatively, an intermittent voltage may be supplied from the DC power supply 28 to the inverter. That is, it is also applicable to the method disclosed in Japanese Patent Application Laid-Open No. 150973/1983.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an inverter device according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the states of points A to W in FIG. 1, and FIG.
FIG. 3 is a waveform diagram showing changes in a pulse width modulated wave when changing the pulse width modulation wave. In the symbols used in the drawings, 10 is an oscillation circuit, 13 is a frequency divider, 14 is a ring counter, and 15 is a logic circuit.

Claims (1)

[Claims] 1. The first of the three-phase bridge type DC-AC converter,
first, second, third, fourth, for controlling the second, third, fourth, fifth and sixth switching elements;
The pulse width modulated wave generation circuit generates the fifth and sixth control signals, and includes an oscillation circuit 10 that generates pulses with a duty ratio of 50% at a predetermined period, and an output of the oscillation circuit 10 that is 1/M( (where M is a positive integer); and first, second, third, fourth, fifth, and sixth ring counter output terminals coupled to the output of the frequency divider 13. a six-stage ring counter 14 having: a first exclusive OR gate 16 connected to the first and second ring counter output terminals; and a first exclusive OR gate 16 connected to the third and fourth ring counter output terminals. a second exclusive OR gate 17; a third exclusive OR gate 18 connected to the fifth and sixth ring counter output terminals; the oscillation circuit 10 and the first exclusive OR gate 16; a first AND gate 19 connected to the oscillation circuit 10 and the second exclusive OR gate 17; a second AND gate 20 connected to the oscillation circuit 10 and the second exclusive OR gate 17; a third AND gate 21 connected to the OR gate 18; and a fourth exclusive AND gate 21 connected to the first AND gate 19 and the second ring counter output terminal.
an OR gate 22; and a fifth exclusive gate connected to the second AND gate 20 and the fourth ring counter output terminal.
an OR gate 23; a sixth exclusive gate connected to the third AND gate 21 and the sixth ring counter output terminal;
an OR gate 24; means for applying the output of the fourth exclusive OR gate 22 as the first control signal to the first switching element 29; a first NOT circuit 25 for obtaining the fourth control signal connected between the second switching element 30;
and means for applying the output of the fifth exclusive OR gate 23 to the third switching element 31 as the third control signal; a second NOT circuit 26 for obtaining the fourth control signal connected between the element 32;
and means for applying the output of the sixth exclusive OR gate 24 to the fifth switching element 33 as the fifth control signal; a third NOT circuit 27 for obtaining the sixth control signal connected between the element 34;
A pulse width modulated wave generation circuit comprising: