JPH0438018A - Error detecting system for relay line - Google Patents
Error detecting system for relay lineInfo
- Publication number
- JPH0438018A JPH0438018A JP14575590A JP14575590A JPH0438018A JP H0438018 A JPH0438018 A JP H0438018A JP 14575590 A JP14575590 A JP 14575590A JP 14575590 A JP14575590 A JP 14575590A JP H0438018 A JPH0438018 A JP H0438018A
- Authority
- JP
- Japan
- Prior art keywords
- parity
- bit
- circuit
- signal
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Landscapes
- Error Detection And Correction (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は中継回路のエラー検出方式、特に、複数ビット
の信号を中継し新たにパリティｂｉｔを生成する回路に
おける中継回路のエラー検出方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error detection method for a relay circuit, and particularly to an error detection method for a relay circuit in a circuit that relays a plurality of bits of signals and newly generates a parity bit.
従来この種のエラー検出、パリティｂｉｔ生 成は、例
えば、Ｌ ｂｉｔの信号Ｓ１〜Ｓ（とそのパリティＰｏ
を入力し、ｊ ｂｉｔの信号Ｓｌ〜Ｓｊとそのパリティ
Ｐｌ、に−ｊｂｉｔの信号Ｓｊや１〜Ｓｍとそのパリテ
ィＰ２ 、 Ｌ −ｋ ｂｉｔの信号Ｓ１＋１〜Ｓεと
そのパリティＰ３を出力する中継回路の場合、第３図の
ように人力信号のエラー検出はｔｂｉｔの信号Ｓ１〜Ｓ
ＥとパリティＰｏのパリティチェックをＥｘ、ＯＲ回路
２−５で行ない、その結果をエラー情報格納レジスタ２
−６に格納し、一方中継、出力信号のパリティは、Ｓ１
〜ＳｔをＳ１〜Ｓ、、Ｓ）や、〜ｓｉｔ、ｓい、〜Ｓε
に分け、バリテ４ ｂｉｔ生成用Ｅｘ．ＯＲ回路２−２
゜２−３．２−４によって生成し、それぞれのパリティ
Ｐ、、Ｐ２．ｐ、を付加して出力していた。Conventionally, this type of error detection and parity bit generation is performed using, for example, L bit signals S1 to S (and their parity Po).
of the relay circuit which inputs the j bit signals Sl to Sj and their parity Pl, -j bit signals Sj, 1 to Sm and their parity P2, and outputs the L -k bit signals S1+1 to Sε and their parity P3. In this case, as shown in Fig. 3, the error detection of the human signal is performed using the tbit signals S1 to S.
Ex and OR circuit 2-5 perform a parity check on E and parity Po, and the result is stored in error information storage register 2.
-6, and the parity of the relay and output signal is S1.
~St as S1~S,,S), ~sit, s, ~Sε
Divided into 4-bit generation Ex. OR circuit 2-2
゜2-3.2-4, and each parity P, , P2 . p, was added and output.
第４図は第３図に示す従来例の詳細を示す回路図であり
、信号１０ｂｉｔ＋パリテイの例を示す。FIG. 4 is a circuit diagram showing details of the conventional example shown in FIG. 3, and shows an example of a signal of 10 bits+parity.
上述した従来の中継回路のエラー検出方式は、入力信号
のパリティチェックに使用するＥｘ、ＯＲ回路２−５と
、中継、出力信号のパリティｂｉｔ生成に使用するＥｘ
、ＯＲ回路２−２．２−３゜２−４を別々に持っている
ためゲート数が多くなり、特に入力信号Ｓｌ〜Ｓｊのｂ
ｉｔ数Ｇが多くなると、Ｅｘ、ＯＲ回路２−５に必要な
ゲート数が飛躍的に増大するので、消費電力の増加やゲ
ートの故障等による回路誤動作の確率が高くなる等の欠
点がある。The error detection method of the conventional relay circuit described above consists of an Ex and OR circuit 2-5 used for parity check of the input signal, and an Ex used for generating a parity bit of the relay and output signal.
, OR circuits 2-2.2-3゜2-4 are separately provided, so the number of gates increases, and especially when the b of input signals Sl to Sj
As the number of ITs G increases, the number of gates required for the Ex and OR circuits 2-5 increases dramatically, resulting in disadvantages such as an increase in power consumption and a high probability of circuit malfunction due to gate failure.
本発明の中継回路のエラー検出方式は、中継。 The relay circuit error detection method of the present invention is a relay circuit.
出力信号のパリティｂｉｔを生成するＥｘ、ＯＲ回路と
、そのＥｘ、ＯＲ回路の出力と入力信号のパリティｂｉ
ｔのＥｘ、ＯＲによって入力信号のパリティチェックを
行なうＥｘ、ＯＲ回路を有している。Ex, OR circuit that generates the parity bit of the output signal, and the output of the Ex, OR circuit and the parity bit of the input signal
It has an Ex and OR circuit that performs a parity check of the input signal by Ex and OR of t.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
図中１−１は入力信号８１〜ＳＬ及びパリティＰｏを格
納するレジスタ、１−２．１−３．１−４はそれぞれ中
継出力信号８１〜ＳＪ 、ＳＪ＋１〜Ｓｋ、Ｓｋや１〜
Ｓεのパリティｂｉｔを生成するＥｘ、ＯＲ回路、１−
５は入力信号及びアリティｂｉｔのパリティチェックに
使用するＥｘ、ＯＲ回路、１−６はＥｘ、ＯＲ回路１−
５の出力を格納する入力信号エラー情報格納レジスタで
ある。In the figure, 1-1 is a register for storing input signals 81-SL and parity Po, and 1-2.1-3.1-4 are relay output signals 81-SJ, SJ+1-Sk, Sk and 1-4, respectively.
Ex, OR circuit that generates parity bit of Sε, 1-
5 is an Ex and OR circuit used for parity check of the input signal and arity bit; 1-6 is an Ex and OR circuit 1-
This is an input signal error information storage register that stores the output of No. 5.
入力信号Ｓ１〜Ｓｊ及びパリティｂｉｔＰｏはレジスタ
１−１に格納され、入力信号Ｓ１〜ＳｊはＳｌ〜ｓ、、
ＳＪ＋１〜Ｓｋ、Ｓい、〜Ｓｉに分けられて出力される
が、このときパリティｂｉｔ生成Ｅｘ、ＯＲ回路１−２
．１−３．１−４によって生成したパリティｂｉｔ Ｐ
ｌ 、 Ｐ２ 、 Ｐ３がそれぞれの出力信号に付加さ
れる。Input signals S1 to Sj and parity bitPo are stored in register 1-1, and input signals S1 to Sj are stored in S1 to Sj, .
It is divided into SJ+1~Sk, S,~Si and output, but at this time, parity bit generation Ex, OR circuit 1-2
．． Parity bit P generated by 1-3.1-4
l, P2, P3 are added to the respective output signals.
一方、パリティチェック実施Ｅｘ、ＯＲ回路１−５は、
パリティｂｉｔ生成Ｅｘ、ＯＲ回路１−２１−３．１−
４の出力と、入力信号のパリティｂｉｔＰ、）の計４
ｂｉｔのＥｘ、・ＯＲによってパリティチェックを行な
い、その結果を入力信号エラー情報格納レジスタ１−６
に格納する。On the other hand, the parity check execution Ex and OR circuit 1-5 are as follows:
Parity bit generation Ex, OR circuit 1-21-3.1-
4 output and input signal parity bit P,), total 4
Parity check is performed by bit Ex, ・OR, and the result is stored in the input signal error information storage register 1-6.
Store in.
第２図は第１図に示す本発明の詳細を示す回路図であり
、信号１０ｂｉｔ＋パリテイの例を示す。FIG. 2 is a circuit diagram showing details of the present invention shown in FIG. 1, and shows an example of a signal of 10 bits+parity.
以上説明したように本発明は、入力された信号ｂｉｔと
パリティｂｉｔのパリティチェックの実施に使用するＥ
ｘ、ＯＲ回路の一部を、入力信号の中継、出力の際に付
加するパリティｂｉｔの生成の際に使用するＥｘ、ＯＲ
回路と共有することにより、ゲート数を削減することが
でき、特に入力信号のｂｉｔ数が多い場合、使用するゲ
ート数の大幅削減により消費電力を低減し信頼性を向上
することができる。As explained above, the present invention provides an E
Ex, OR, which uses part of the x, OR circuit to generate parity bits that are added when relaying and outputting input signals
By sharing the gates with the circuit, the number of gates can be reduced, and especially when the number of bits of the input signal is large, the number of gates used can be significantly reduced, reducing power consumption and improving reliability.
第１図は本発明の一実施例を示すブロック図、第２図は
第１図の詳細を示す回路図、第３図は従来の一例を示す
ブロック図、第４図は第３図の詳細を示す回路図である
。
１−１・・・入力信号、パリティ格納レジスタ、１−２
〜１−４・・・中継出力信号パリティ生成Ｅｘ。
ＯＲ回路、１−５・・・入カ信号パリティチェックＥｘ
、ＯＲ回路、１−６・・・入力信号エラー情報格納レジ
スタ、２−１・・・入カ信号、パリティ格納レジスタ、
２−２へ２−４・・・中継出方信号パリティ生成Ｅｘ、
ＯＲ回路、２−５・・・入力信号パリティチェックＥｘ
、ＯＲ回路、２−６・・・入力信号エラー情報格納レジ
スタ。Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing details of Fig. 1, Fig. 3 is a block diagram showing a conventional example, and Fig. 4 is a detail of Fig. 3. FIG. 1-1...Input signal, parity storage register, 1-2
~1-4... Relay output signal parity generation Ex. OR circuit, 1-5...Input signal parity check Ex
, OR circuit, 1-6... Input signal error information storage register, 2-1... Input signal, parity storage register,
To 2-2 2-4... Relay output signal parity generation Ex,
OR circuit, 2-5...Input signal parity check Ex
, OR circuit, 2-6... Input signal error information storage register.
Claims (1)
和（以下Ｅｘ．ＯＲという）によって得られるビット（
以下パリテイｂｉｔ又はパリテイという）を入力し、該
信号ビットにパリテイｂｉｔを加えた全ビットをＥｘ．
ＯＲしてエラー検出（以下パリテイチェックという）を
するとともに、該信号ビットの中継を行ない、その際に
新たにパリテイｂｉｔを生成し、信号ビットに付加して
出力する中継回路のエラー検出方式において、入力され
た信号ビットとパリテイｂｉｔのパリテイチェックの際
に使用するＥｘ．ＯＲ回路の一部を、該信号の中継、出
力の際に付加するパリテイｂｉｔの生成に使用するＥｘ
．ＯＲ回路と共有することを特徴とする中継回路のエラ
ー検出方式。The bit (hereinafter referred to as Ex.OR) obtained by the exclusive OR (hereinafter referred to as Ex.OR) of a multi-bit signal and all bits of the signal
Parity bit (hereinafter referred to as parity) is input, and all bits obtained by adding the parity bit to the signal bit are Ex.
In the error detection method of the relay circuit, which performs error detection (hereinafter referred to as parity check) by ORing, and also relays the signal bit, generates a new parity bit at that time, adds it to the signal bit, and outputs it. , Ex. used for parity check of input signal bits and parity bits. A part of the OR circuit is used to generate a parity bit to be added when relaying and outputting the signal.
．． An error detection method for a relay circuit characterized by being shared with an OR circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14575590A JPH0438018A (en) | 1990-06-04 | 1990-06-04 | Error detecting system for relay line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14575590A JPH0438018A (en) | 1990-06-04 | 1990-06-04 | Error detecting system for relay line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0438018A true JPH0438018A (en) | 1992-02-07 |
Family
ID=15392409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14575590A Pending JPH0438018A (en) | 1990-06-04 | 1990-06-04 | Error detecting system for relay line |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438018A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007173359A (en) * | 2005-12-20 | 2007-07-05 | Fdk Corp | Trance |
| JP2008171880A (en) * | 2007-01-09 | 2008-07-24 | Fdk Corp | Trance |
| JP2009026915A (en) * | 2007-07-19 | 2009-02-05 | Fdk Corp | Trance |
-
1990
- 1990-06-04 JP JP14575590A patent/JPH0438018A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007173359A (en) * | 2005-12-20 | 2007-07-05 | Fdk Corp | Trance |
| JP2008171880A (en) * | 2007-01-09 | 2008-07-24 | Fdk Corp | Trance |
| JP2009026915A (en) * | 2007-07-19 | 2009-02-05 | Fdk Corp | Trance |
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