JPH0438019B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <<Industrial Application Field>> The present invention relates to an improvement in a coordinate conversion circuit used in image processing devices to enlarge, reduce, rotate, etc. an image.

<<Prior art>> In order to realize enlargement, reduction, rotation, etc. of an image in an image processing device, it is necessary to perform coordinate transformation, such as affine transformation, and read out the image memory using the transformed address. . Affin transformation from coordinates (x ₁ + y ₁ ) to coordinates (x ₂ , y ₂ ) is expressed by the following equation.

x ₂ = ax ₁ + by ₁ + c y ₂ = dx ₁ + ey ₁ + f... (1) Figure 2 shows a conventional hardware-based coordinate transformation circuit for performing affine transformation in real time on a raster scan type imaging device. shows. Data input of coefficients a, c/b, and b (hereinafter a, c/c/
(referred to as b, b) is input and held. The contents of the x counter 4 are incremented every x clock of the raster scan, and the x coordinate is output. A coefficient multiplier 5 multiplies the output a from the a register 1 and the output from the x counter 4, and outputs a.x. The y counter 6 converts the output c/b from the c/b register 2 into a y synchronization signal (1 pulse/1 image)
After loading at the timing, +1 is added for each raster scan row by the x synchronization signal, so the output becomes y+c/b. The coefficient multiplier 7 multiplies the output b from the b register 3 and the output y+c/b from the y counter 6 to obtain b・
Output y+c. Adder 8 is the coefficient multiplier 5
The output a・x from the coefficient multiplier 7 and the output b・x from the coefficient multiplier 7
y+c, and the affine transformation output a・x+
Output b・y+c.

Although the coordinate transformation circuit having such a configuration is capable of real-time coordinate transformation, it has the drawback of requiring large-scale hardware, such as the use of complex and expensive high-speed multipliers.

Patent application filed in 1983 for an improved version of the above coordinate conversion circuit.
There is a coordinate conversion circuit disclosed in No. 74635 (Japanese Unexamined Patent Publication No. 59-200373), but the circuit configuration is not simple enough, such as requiring two sets of output registers.

≪Problems to be Solved by the Invention≫ The present invention has been made to solve the above-mentioned problems. The purpose is to

<<Means for solving the problem>> The coordinate conversion circuit of the first aspect of the present invention is a raster conversion circuit.
Selection means for selecting one of three types of data inputs determined by the period and signal width of the coefficient a, b, c, x synchronization signal in response to the x, y synchronization signal from the scan type image processing device; A two-input adder takes one of the outputs from the selection means and outputs it in synchronization with the pixel clock, and the output from this adder is held and the output is sent to the other adder with a delay of one pixel clock. It is characterized by comprising a register serving as an input, and outputting ax+by+c from the register corresponding to the x, y coordinates of the image scanning position.

The coordinate conversion circuit according to the second aspect of the present invention is a raster conversion circuit.
selection means for selecting one of four types of data inputs determined by the period and signal width of the coefficients a, b, c, d, x synchronization signal in response to the synchronization signal from the scan type image processing device; A two-input adder whose one input is the output from the selection means and outputs in synchronization with the pixel clock; and a two-input adder that holds the output from this adder and, after one pixel clock delay, outputs the output to the other input of the adder. with a coefficient d
is a value that takes into account the deviation of one line in the y direction with respect to the coefficient c, and from the register, ax
Outputs +by+c and ax+by+ for odd fields
It is characterized by outputting d.

<<Operation>> In the coordinate conversion circuit of the first aspect of the present invention, the data is input from the register corresponding to the x and y coordinates of the image scanning position.
It is possible to output ax+by+c.

In the coordinate conversion circuit according to the second aspect of the present invention, from the register, corresponding to the x and y coordinates of the image scanning position,
By outputting ax+by+c for even fields and ax+by+d for odd fields, it is also possible to support image scanning in interlaced mode.

≪Example≫ The present invention will be explained in detail below using the drawings.

FIG. 1 is a block diagram showing an embodiment of a coordinate conversion circuit according to the present invention. 11,12,1
3 is the coefficients a, b, c from the control computer etc.
Coefficient registers a, b', c' of three-state outputs input and hold data inputs a, b', c' related to the selection means constitute the selection means; 14 is the coefficient register 11, 12, 13 An adder which takes one of these as one input, 15 is this adder 1
a 3-state output F register 1 that holds the output of 4 and uses the output as the other input of the adder 14;
Reference numeral 6 inputs an x, y synchronizing signal, which is a synchronizing signal from a raster scan type image device, and a pixel clock, selects a register among the coefficient registers 11, 12, and 13, and outputs the adder 14 and the F register 15. A control circuit 17 for performing control is a pull-up resistor connected to the other input of the adder 14.

FIG. 3 is a time chart showing the operation of each part of the coordinate conversion circuit configured as described above in the case of 6 strokes in the x direction and a 4 pixel clock in the x synchronization width. In raster scan, pixels are scanned in the x direction in accordance with the pixel clock, and an x synchronization signal pulse low is generated every time one row is scanned.
A y synchronization signal pulse is generated every time the image scan is completed.

Coefficient registers 11, 12, and 13 respectively input and hold coefficients a, b', and c' from a control computer or the like. However, b′=b−ha, c′=c−ga−
b′. Here h = x period - 1 (pixel clock), g =
In the case of FIG. 3, x synchronization width is -1 (pixel clock), x period = 10 (pixel clock), and x synchronization width = 4 (pixel clock), so h = 9 and g = 3.

When the y synchronization signal is L, the register selection signal from the control circuit 16 causes the A input of the adder 14 to
c' register 13 is selected (FIG. 3D). Since the output of the F register 15 is disabled (disconnected) (Fig. 3), all B inputs of the adder 14 become H due to the pull-up resistor 17 (Fig. 3).
Figure H). Since the carry input c _o becomes H, the output of the adder 14 becomes F=c' (FIG. 3). The value of c' is held in the F register 15 (FIG. 3).

Next, when the y synchronization signal becomes H and the x synchronization signal becomes L, from the first pixel clock (period t) in the synchronization width of the x synchronization signal to the point one clock before the last, the A input of the adder 14 is applied. is a register 11
is selected, F register 15 is output enabled,
The carry input of the adder 14 becomes L, and the adder 14
The output of is F=c′+〓a.

Then, at the last clock in the synchronization width of the x synchronization signal, the b' register 12 is selected for the A input of the adder 14. The output of the adder 14 is F=b'+
c'+ga=c, and as a result, the coefficient c is held in the F register 15 at the next clock.

Next, when the x synchronization signal becomes H, the adder 14
The a register 11 is selected as the input of F=c+
= a. The output F of the adder 14 is output from the F register 15 with a delay of one clock.

Next, when the x synchronization signal becomes L, adder 1
The a register 11 is selected as the A input of 4, and a is sequentially added to it, but at the time of the last clock, b' and the register 12 are selected as the a input. At this time, the addition output becomes F=c+ha+b'=b+c, and b+c is held in the F register 15 at the next clock.

Thereafter, addition is repeated in the same way, and when both the y synchronization signal and the x synchronization signal are H, that is, when actually accessing the image memory, a is added for each clock, and the value obtained by adding b for each line is obtained. It is output from the F register 15. That is, the output of the F register 15 corresponding to the x, y coordinates of the image scanning position is ax+by+c.

According to the coordinate conversion circuit configured as described above, the configuration is simple as there is only one output register, and
Control logic is also simplified.

In the above embodiment, a three-state element register is used as the A input selection means of the adder 14, but the present invention is not limited to this, and a multiplexer, a wired OR using an open collector element, etc. can be used as well.

Also, instead of an adder, an ALU (arithmetic logic operation circuit)
may also be used. In this case, the coefficient is stored in the F register.
At the time when c' is held (when the y synchronization signal is L)
Set the function of ALU to F=A, and at other times F
=A+B. If such a configuration is used, the pull-up resistor 17 becomes unnecessary, and the F register 15 also becomes unnecessary to provide three-state output.

FIG. 4 is a block diagram showing a second embodiment of the coordinate conversion circuit according to the present invention, which can process scanned images in interlaced mode. Components that are the same as those in FIG. 1 are designated by the same reference numerals and their explanation will be omitted. 18 is one of the selection means, and d' register is given input data d' = d-ga-b' from a control computer, etc.; 19 is (interlaced
This control circuit is designed to input an even-odd field signal in addition to the x, y synchronizing signal and pixel clock, which are synchronizing signals from a raster scan type imager (of the same mode). The basic operation of this circuit is the same as the embodiment shown in Figure 1, except that in interlace mode, the c' register and d' register (both registers for offset coefficients) are used alternately in response to field switching. are different. In other words, in an even field where only the even numbered scan lines are processed during screen scanning, the even field signal
c' register is selected and the output of F register 15 is
It becomes ax+by+c. In odd fields where only odd scan lines are processed, the d' register is similarly selected and the output of the F register 15 is ax+by+
d. Here, the coefficient d is a value that takes into account a shift of one line in the y direction. By using a coordinate conversion circuit having such a configuration, coordinate conversion can be performed even in interlaced mode image scanning.

<<Effects of the Invention>> As described above, according to the present invention, a coordinate transformation circuit capable of real-time affine transformation can be realized with a simple configuration using less hardware and simple control logic. It can also be applied to scanned images in interlaced mode.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a coordinate conversion circuit according to the present invention, FIG. 2 is a block diagram of an example of a conventional coordinate conversion circuit, and FIG. 3 is an operation of the coordinate conversion circuit of FIG. 1. FIG. 4 is a block diagram of a second embodiment of the coordinate conversion circuit according to the present invention. a, b', c', d...data input, 11, 12, 1
3, 18...Selection means, 14...Adder, 15...Register.

Claims (1)

[Claims] 1 x from a raster scan type image processing device,
selection means for selecting one of the three types of data inputs determined by the period and signal width of the coefficients a, b, c, and x synchronization signals corresponding to the y synchronization signal; a two-input adder that takes the input as input and outputs it in synchronization with the pixel clock, and a register that holds the output from this adder and whose output becomes the other input of the adder after one pixel clock delay; A coordinate conversion circuit characterized in that the register outputs ax+by+c corresponding to the x and y coordinates of the scanning position. 2 Selection means for selecting one of four types of data inputs determined by the period and signal width of the coefficients a, b, c, d, x synchronization signal in response to the synchronization signal from the raster scan type image processing device and a two-input adder which takes the output from this selection means as one of its inputs and outputs it in synchronization with the pixel clock; and a two-input adder that holds the output from this adder and delays it by one pixel clock and sends the output to the adder. The coefficient d is set to a value that takes into account the deviation of one line in the y direction from the coefficient c, and the register is set to a value that takes into account the deviation of one line in the y direction from the coefficient c. Outputs ax+by+c, and for odd fields, ax+
A coordinate conversion circuit characterized by outputting by+d.