JPH0438080U - - Google Patents
Info
- Publication number
- JPH0438080U JPH0438080U JP8140690U JP8140690U JPH0438080U JP H0438080 U JPH0438080 U JP H0438080U JP 8140690 U JP8140690 U JP 8140690U JP 8140690 U JP8140690 U JP 8140690U JP H0438080 U JPH0438080 U JP H0438080U
- Authority
- JP
- Japan
- Prior art keywords
- laminate
- main surfaces
- chip
- connection component
- type multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000605 extraction Methods 0.000 claims 3
- 238000010030 laminating Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Description
第１図ａ〜ｃは、それぞれ、本考案の一実施例
に用いられる接続基板の各平面図、第２図は配線
の一例を説明するための模式図、第３図は接続基
板を積層して得られた積層体を示す側面図、第４
図は本考案の一実施例にかかるチツプ型多層接続
部品を示す斜視図、第５図はプリント回路基板上
に多層接続部品を実装した状態を示す略図的平面
図、第６図ａ及びｂは、それぞれ、接続基板の変
形例を説明するための各平面図、第７図ａ〜ｄは
、それぞれ、接続基板のさらに他の変形例を説明
するための各平面図であり、第７図ｅは形成され
る配線パターンの一例を示す模式図、第８図は本
考案のチツプ型多層接続部品の他の例の平面図、
第９図は接続基板のさらに他の例を示す平面図、
第１０図及び第１１図は、本考案のチツプ型多層
接続部品のさらに他の例を示す各斜視図である。
図において、１１〜１３は接続基板、１７ａ〜
１７ｄは導電路、１９は積層体、２０ａ〜２０ｈ
は端子電極、２１はチツプ型多層接続部品を示す
。
Figures 1 a to c are respective plan views of connection boards used in one embodiment of the present invention, Figure 2 is a schematic diagram for explaining an example of wiring, and Figure 3 is a diagram illustrating a stack of connection boards. 4th side view showing the laminate obtained by
The figure is a perspective view showing a chip-type multilayer connection component according to an embodiment of the present invention, FIG. 5 is a schematic plan view showing a state in which the multilayer connection component is mounted on a printed circuit board, and FIGS. 6a and 6b are , FIGS. 7a to 7d are plan views for explaining still other modifications of the connection board, and FIG. 8 is a schematic diagram showing an example of a wiring pattern to be formed, and FIG. 8 is a plan view of another example of the chip-type multilayer connection component of the present invention.
FIG. 9 is a plan view showing still another example of the connection board;
FIGS. 10 and 11 are perspective views showing still other examples of the chip-type multilayer connection component of the present invention. In the figure, 11-13 are connection boards, 17a-
17d is a conductive path, 19 is a laminate, 20a to 20h
Reference numeral 21 indicates a terminal electrode, and 21 indicates a chip-type multilayer connection component.
Claims (1)
縁近傍に形成されており、引出し電極のうち少な
くとも２個の引出し電極間を接続する少なくとも
１本の導電路が一方主面に形成された接続基板を
複数枚積層してなる積層体と、該積層体の側面に
形成されており、前記引出し電極に接続された端
子電極とを備えることを特徴とする、チツプ型多
層接続部品。 A plurality of extraction electrodes are formed near the outer periphery of at least one of the main surfaces, and at least one conductive path connecting at least two of the extraction electrodes is connected to a connection substrate formed on one of the main surfaces. A chip-type multilayer connection component comprising: a laminate formed by laminating a plurality of sheets; and a terminal electrode formed on a side surface of the laminate and connected to the extraction electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8140690U JPH0438080U (en) | 1990-07-30 | 1990-07-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8140690U JPH0438080U (en) | 1990-07-30 | 1990-07-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0438080U true JPH0438080U (en) | 1992-03-31 |
Family
ID=31627325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8140690U Pending JPH0438080U (en) | 1990-07-30 | 1990-07-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438080U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2023519145A (en) * | 2020-03-23 | 2023-05-10 | クアルコム，インコーポレイテッド | A package including a substrate and a high density interconnect integrated device bonded to the substrate |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5544776A (en) * | 1978-09-26 | 1980-03-29 | Matsushita Electric Industrial Co Ltd | Printed circuit board |
| JPS55158693A (en) * | 1979-05-30 | 1980-12-10 | Fujitsu Ltd | Hybrid integrated circuit |
| JPS5739461B2 (en) * | 1975-06-12 | 1982-08-21 | ||
| JPS5911577B2 (en) * | 1979-04-04 | 1984-03-16 | メルク・シヤ−プ・エンド・ド−ム（アイ・エ−）コ−ポレ−シヨン | Amino derivative of 2-hydroxy-6,9-methano-11-amino-5,6,7,8,9,10-hexahydro-benzocyclooctene |
| JPS6388773A (en) * | 1986-10-01 | 1988-04-19 | 松下電器産業株式会社 | Joint of magnet wire and lead wire |
-
1990
- 1990-07-30 JP JP8140690U patent/JPH0438080U/ja active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5739461B2 (en) * | 1975-06-12 | 1982-08-21 | ||
| JPS5544776A (en) * | 1978-09-26 | 1980-03-29 | Matsushita Electric Industrial Co Ltd | Printed circuit board |
| JPS5911577B2 (en) * | 1979-04-04 | 1984-03-16 | メルク・シヤ−プ・エンド・ド−ム（アイ・エ−）コ−ポレ−シヨン | Amino derivative of 2-hydroxy-6,9-methano-11-amino-5,6,7,8,9,10-hexahydro-benzocyclooctene |
| JPS55158693A (en) * | 1979-05-30 | 1980-12-10 | Fujitsu Ltd | Hybrid integrated circuit |
| JPS6388773A (en) * | 1986-10-01 | 1988-04-19 | 松下電器産業株式会社 | Joint of magnet wire and lead wire |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2023519145A (en) * | 2020-03-23 | 2023-05-10 | クアルコム，インコーポレイテッド | A package including a substrate and a high density interconnect integrated device bonded to the substrate |
| JP2025166172A (en) * | 2020-03-23 | 2025-11-05 | クアルコム，インコーポレイテッド | Package including a substrate and a high density interconnect integrated device coupled to the substrate - Patent Application 20070122997 |
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