JPH0438123U - - Google Patents
Info
- Publication number
- JPH0438123U JPH0438123U JP8099790U JP8099790U JPH0438123U JP H0438123 U JPH0438123 U JP H0438123U JP 8099790 U JP8099790 U JP 8099790U JP 8099790 U JP8099790 U JP 8099790U JP H0438123 U JPH0438123 U JP H0438123U
- Authority
- JP
- Japan
- Prior art keywords
- attenuation
- circuit
- input terminal
- signal
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013016 damping Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Attenuators (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
第１図は、本考案の一実施例を示す回路図、第
２図はバランス調整回路を示す回路図、第３図は
それに用いられている従来の信号減衰回路を示す
回路図、第４図はアツプダウンカウンタ及びデコ
ーダの一例を示す回路図、及び第５図は制御信号
と減衰量との関係を示す図である。
３６，５９……第１減衰部、３７〜４０，４７
〜５０……抵抗、４６，６２……第２減衰部、４
１〜４４，５１〜５４……スイツチ、５６，５７
……第１、第２減衰回路、６１……オフセツト抵
抗。
Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a balance adjustment circuit, Fig. 3 is a circuit diagram showing a conventional signal attenuation circuit used therein, and Fig. 4 is a circuit diagram showing an embodiment of the present invention. 5 is a circuit diagram showing an example of an up-down counter and a decoder, and FIG. 5 is a diagram showing the relationship between a control signal and an attenuation amount. 36, 59...first damping section, 37-40, 47
~50...Resistance, 46,62...Second damping section, 4
1-44, 51-54...Switch, 56, 57
...First and second attenuation circuits, 61...Offset resistor.
Claims (1)
配置される第１及び第２減衰回路と、前記第１及
び第２減衰回路の減衰量を同時にかつ逆方向に変
化させる制御回路とから成る信号減衰回路であつ
て、 前記第１及び第２減衰回路は、直列接続された
複数の抵抗及び該抵抗の一端を共通接続点に接続
する為の複数のスイツチとから成る第１減衰部と
、該第１減衰部の出力端に接続された第１バツフ
ア回路と、直列接続された複数の抵抗及び該抵抗
の一端を共通接続点に接続する為の複数のスイツ
チとから成り、入力端が前記第１バツフア回路に
接続された第２減衰部と、該第２減衰部の出力端
に接続された第２バツフア回路とにより構成され
、 前記第１減衰回路の入力端は、一方の信号入力
端子に直接接続され、前記第２減衰回路の入力端
は、他方の信号入力端子にオフセツト抵抗を介し
て接続されることを特徴とする信号減衰回路。 (2) 前記第１及び第２減衰部を構成する抵抗は
、所定の重み付けが成されており、前記オフセツ
ト抵抗は、前記重み付けが成された抵抗により設
定される最小のステツプが得られる値に設定され
ることを特徴とする請求項第１項記載の信号減衰
回路。[Claims for Utility Model Registration] (1) First and second attenuation circuits disposed on one and the other of the left and right channels, respectively, and changing the attenuation amounts of the first and second attenuation circuits simultaneously and in opposite directions. and a control circuit, wherein the first and second attenuation circuits each include a plurality of resistors connected in series and a plurality of switches for connecting one end of the resistor to a common connection point. A first attenuation section, a first buffer circuit connected to the output end of the first attenuation section, a plurality of resistors connected in series, and a plurality of switches for connecting one end of the resistors to a common connection point. , a second attenuation section whose input end is connected to the first buffer circuit, and a second buffer circuit connected to the output end of the second attenuation section, the input end of the first attenuation circuit is A signal attenuation circuit, characterized in that the second attenuation circuit is directly connected to one signal input terminal, and the input terminal of the second attenuation circuit is connected to the other signal input terminal via an offset resistor. (2) The resistances constituting the first and second damping sections are weighted in a predetermined manner, and the offset resistance is set to a value that provides the minimum step set by the weighted resistances. 2. The signal attenuation circuit according to claim 1, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8099790U JP2509520Y2 (en) | 1990-07-30 | 1990-07-30 | Signal attenuation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8099790U JP2509520Y2 (en) | 1990-07-30 | 1990-07-30 | Signal attenuation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0438123U true JPH0438123U (en) | 1992-03-31 |
| JP2509520Y2 JP2509520Y2 (en) | 1996-09-04 |
Family
ID=31626543
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8099790U Expired - Lifetime JP2509520Y2 (en) | 1990-07-30 | 1990-07-30 | Signal attenuation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2509520Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016082504A (en) * | 2014-10-21 | 2016-05-16 | ローム株式会社 | Variable gain amplifier circuit |
-
1990
- 1990-07-30 JP JP8099790U patent/JP2509520Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016082504A (en) * | 2014-10-21 | 2016-05-16 | ローム株式会社 | Variable gain amplifier circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2509520Y2 (en) | 1996-09-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |