JPH0470000U - - Google Patents
Info
- Publication number
- JPH0470000U JPH0470000U JP11284890U JP11284890U JPH0470000U JP H0470000 U JPH0470000 U JP H0470000U JP 11284890 U JP11284890 U JP 11284890U JP 11284890 U JP11284890 U JP 11284890U JP H0470000 U JPH0470000 U JP H0470000U
- Authority
- JP
- Japan
- Prior art keywords
- attenuation
- buffer circuit
- section
- circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013016 damping Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Attenuators (AREA)
Description
第１図は、本考案の一実施例を示す回路図、第
２図はバランス調整回路を示す回路図、第３図は
それに用いられている従来の信号減衰回路を示す
回路図、第４図は従来のアツプダウンカウンタ及
びデコーダの一例を示す回路図、第５図は本考案
のアツプダウンカウンタ及びデコーダの説明に供
する為の回路図、及び第６図は制御信号と減衰量
の関係を示す回路図である。
３６，６４……減衰部、４１，６５……バツフ
ア回路、４２，６６……第１減衰部、５１，６７
……第１バツフア回路、５２，６８，……第２減
衰部、６１，６９……第２バツフア回路、７０…
…デコーダ。
Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a balance adjustment circuit, Fig. 3 is a circuit diagram showing a conventional signal attenuation circuit used therein, and Fig. 4 is a circuit diagram showing an embodiment of the present invention. 5 is a circuit diagram showing an example of a conventional up-down counter and decoder, FIG. 5 is a circuit diagram for explaining the up-down counter and decoder of the present invention, and FIG. 6 shows the relationship between the control signal and the attenuation amount. It is a circuit diagram. 36, 64... Attenuation section, 41, 65... Buffer circuit, 42, 66... First attenuation section, 51, 67
...First buffer circuit, 52, 68, ...Second attenuation section, 61, 69...Second buffer circuit, 70...
…decoder.
Claims (1)
配置される第１及び第２減衰回路と、前記第１及
び第２減衰回路の減衰量を同時にかつ逆方向に変
化させる制御回路とから成る信号減衰回路であつ
て、 前記第１及び第２減衰回路は、入力信号を減衰
又はそのまま通過させる減衰部と、該減衰部の出
力端に接続されたバツフア回路と、直列接続され
た複数の抵抗及び該抵抗の一端を共通接続点に接
続する為の複数のスイツチとから成り前記バツフ
ア回路の出力信号が印加される第１減衰部と、該
第１減衰部の出力端に接続された第１バツフア回
路と、直列接続された複数の抵抗及び該抵抗の一
端を共通接続点に接続する為の複数のスイツチと
から成り、入力端が前記第１バツフア回路に接続
された第２減衰部と、該第２減衰部の出力端に接
続された第２バツフア回路とにより構成されるこ
とを特徴とする信号減衰回路。 (2) 前記第１及び第２減衰部を構成する抵抗は
、所定の重み付けが成されており、前記減衰部の
減衰量は、前記重み付けが成された抵抗により設
定される最小のステツプが得られる値に設定され
ることを特徴とする請求項第１項記載の信号減衰
回路。[Claims for Utility Model Registration] (1) First and second attenuation circuits disposed on one and the other of the left and right channels, respectively, and changing the attenuation amounts of the first and second attenuation circuits simultaneously and in opposite directions. and a control circuit, the first and second attenuation circuits are connected in series with an attenuation section that attenuates or passes the input signal as is, and a buffer circuit connected to the output end of the attenuation section. a first attenuation section to which the output signal of the buffer circuit is applied, which is made up of a plurality of resistors and a plurality of switches for connecting one end of the resistor to a common connection point; A first buffer circuit connected to the first buffer circuit, a plurality of resistors connected in series, and a plurality of switches for connecting one end of the resistor to a common connection point, the input end of which is connected to the first buffer circuit. 1. A signal attenuation circuit comprising: a second attenuation section; and a second buffer circuit connected to an output end of the second attenuation section. (2) The resistances constituting the first and second damping sections are weighted in a predetermined manner, and the attenuation amount of the damping section is such that the minimum step set by the weighted resistances is obtained. 2. The signal attenuation circuit according to claim 1, wherein the signal attenuation circuit is set to a value equal to or less than 100%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11284890U JPH0470000U (en) | 1990-10-26 | 1990-10-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11284890U JPH0470000U (en) | 1990-10-26 | 1990-10-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0470000U true JPH0470000U (en) | 1992-06-22 |
Family
ID=31860374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11284890U Pending JPH0470000U (en) | 1990-10-26 | 1990-10-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0470000U (en) |
-
1990
- 1990-10-26 JP JP11284890U patent/JPH0470000U/ja active Pending
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