JPH0438290B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a capacitive converter that converts a physical quantity such as differential pressure into an electrical signal via capacitance, and particularly improves the conversion accuracy of the physical quantity. Regarding capacitive converters.

(Prior art) Figure 8 is from 1985, which is the basis for the improvement of the present invention.
1 is a block diagram of a capacitive converter disclosed in Japanese Patent Application No. 60-283715 (title of invention: capacitive converter) filed on December 17th.

Resistors R ₁ and R ₂ are connected between the non-inverting input terminal (+) and the output terminal of the operational amplifier Q ₁ , and the inverting input terminal (-) resistors the constant voltage V ₀ and the voltage at the output terminal. A voltage divided by R ₃ and R ₄ is applied.

The output terminal of operational amplifier Q ₁ is connected to the input terminal of inverter G ₁ , and its output terminal is connected to the connection point of resistors R ₁ and R ₂ via resistor R ₅ , and the variable capacitor is connected via inverter G ₂ . ₁ is connected to one end. The other end of the variable capacitor C ₁ is connected to the common potential point COM via the capacitor C ₂ and is connected to the operational amplifier Q ₁
is connected to the non-inverting input terminal (+) of

Note that operational amplifier Q ₁ and inverters G ₁ and G ₂ are energized with positive voltage +E, and inverters G ₁ and G ₂ are
Consists of CMOS transistors.

Next, the operation of the embodiment shown in FIG. 8 constructed as above will be explained using the waveform diagram shown in FIG. 9.

When the voltage _V4 at the output end of the inverter _G1 is at the high level shown in Figure 9D, the inverter
The output of G ₂ is low level, and variable capacitor C ₁ and capacitor C ₂ are charged through resistor R ₂ , and the operational amplifier
The potential at the input terminal of _Q1 rises as shown in period _T1 in FIG. 9A. Along with this, the voltage V ₃ at the output terminal of the operational amplifier Q ₁ (FIG. 9C) and the voltage V ₂ at the connection between the resistors R ₁ and R ₂ (FIG. 9 B) also rise. When the voltage _V3 exceeds the threshold voltage _VTH of the inverter _G1 , the level of its output terminal is inverted to low level. Therefore, the output terminal of inverter G ₂ becomes high level, and the voltage divided by variable capacitance C ₁ and capacitance C ₂ is applied to the non-inverting input terminal (+) of operational amplifier Q ₁ , and the voltage V ₁ rises vertically (Figure 9a). After that, since the output terminal of inverter _G1 is at low level, variable capacitance _C1 and electrostatic capacitance _C2 are connected via resistor _R2.
The charge continues to discharge during the period T ₂ shown in Fig. 9A,
The potential at the non-inverting input terminal (+) of operational amplifier _Q1 decreases. When the threshold voltage _VTH at the input end of inverter _G1 is reached, its output end is inverted to high level and returns to its original state. Therefore, the current flowing through the resistor R ₂ becomes a constant current i _c in the forward and reverse directions in response to the level change of the voltage V ₄ at the output terminal of the inverter G ₁ . Therefore, oscillation as shown in FIG. 9 continues.

A quantitative explanation of the above points is as follows.
Voltages V ₁ to V ₄ satisfy the following relationship.

V ₄ −V ₂ /R ₅ =V ₂ −V ₁ /R ₂ +V ₂ −V ₃ /R ₁ (1) V ₃ = (1+R ₄ /R ₃ )V ₁ −R ₄ /R ₃ V ₀ (2 ) From the relationship of equations (1) and (2), V ₂ = R ₀ /R ₅ V ₄ −R ₀ /R ₁・R ₄ /R ₃ V ₀ + (1/R ₂ +1/R ₁ +
R ₄ /R ₁ R ₃ ) R ₀ V ₁ (3). However, R ₀ =1/R ₅ +1/R ₁ +1/R ₂ .

Here, if R ₅ /R ₁ =R ₃ /R ₄ is selected, V ₂ −V ₁ =R ₀ /R ₅ (V ₄ −V ₀ ) (4). Here, the voltage is constant so that V ₀ = E/2
When V ₀ is determined, V ₂ −V ₁ =R ₀ /R ₅ (V ₄ −E/2) (4)'. Therefore, since the voltage V ₄ repeats two levels of +E←→zero, the current i flowing through the resistor R ₂ is: i _C = |V ₂ −V ₁ |/R ₂ = R ₀ /R ₂ R ₅ A constant current flows in both directions with a magnitude of |E/2| (5).

Note that in order to prevent oscillation in the operational amplifier _Q1 , the amount of positive feedback is reduced by selecting _R2 >> _R4 .

Next, when considering the charge fluctuation in the variable capacitor _C1 , the following equation holds true.

T ₁ ·i _C =C ₁ E (6) Therefore, the period T ₁ is obtained as T ₁ =C ₁ /i _C (6)', and the same is true for the period T ₂ . Therefore, the frequency at the output end of the inverter _G1 has a value proportional to the variable capacitance _C1 .

(Problem to be Solved by the Invention) However, in the conventional capacitive converter shown in _FIG . There is a problem that the amount decreases.

(Means for Solving the Problems) In order to solve the above problems, the present invention includes a variable capacitor whose capacitance changes depending on the physical quantity to be detected, and one end of this capacitor connected to a non-inverting input terminal. An operational amplifier has an inverting input terminal applied with a divided voltage of the output terminal voltage and a constant voltage, and the output terminal of this operational amplifier is applied to the input terminal, and the output terminal voltage is converted to the inverted phase of that voltage through a logic element. an inverter that is applied to the other end of the variable capacitor, a switching means that uses a switch to switch the constant current value that is applied to the non-inverting input end of the operational amplifier from the voltage division point between the output of the operational amplifier and the output of the inverter, and this switch. The structure includes a microcomputer having a correction means that calculates and corrects the slew rate of the operational amplifier by switching based on a signal, and a calculation means that calculates a physical quantity from a frequency related to the output frequency of the inverter.

(Function) With this configuration, the slew rate of the operational amplifier can be measured with a microcomputer, and based on this measurement result, a correction calculation can be performed on the period obtained from the output of the inverter. It is possible to output electrical signals that accurately correspond to physical quantities.

(Example) Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing a capacity/time converter 10 according to an embodiment of the present invention. Furthermore, the 8th
Components having the same functions as those of the conventional technology shown in the figures are given the same reference numerals, and their explanations will be omitted as appropriate.

In Figure 1, resistors R 2 _and R ₆ are connected between the non-inverting input terminal (+) of operational amplifier Q ₁ and the connection point of resistors R ₁ and R ₅ .
This converter is different from the capacitive converter shown in FIG. 8 in that the converter and a switch for switching these are connected in series, and the switch SW is switched by a selection signal A.

Therefore, while the selection signal A shown in Fig. 2A is held at a high level, the switch SW is connected to the resistor _R2 side, and the circuit becomes the same as that shown in Fig. 8, so that the operational amplifier _Q1 is not inverted. The voltage V ₁ at the input end (+) and the voltage V ₄ at the output end of the inverter G ₁ result in the waveforms shown in FIG. 2 B and C, similar to those in FIG. 9. When the selection signal A becomes low level (Fig. 2 A), the switch
SW is connected to the _R6 side, but operates in the same way as when the selection signal A is at high level, only the oscillation period is different.

Therefore, from this difference in oscillation period, the response delay time t _d due to the slew rate of operational amplifier Q ₁
is calculated using Figure 3.

The third image is an enlarged waveform of Figure 2 (b).
V′ _TH is the threshold voltage of operational amplifier Q ₁ . Now, if the resistance R ₂ is the value obtained by multiplying the resistance R ₆ by the coefficient k, then R ₂ = kR ₆ (7), and accordingly, the value is proportional to the variable capacitance C ₁ corresponding to the resistances R ₂ and R ₆ . The relationship between the periods t ₁ and t ₁ ′ is t ₁ = kt ₁ ′ (8). Therefore, from equations (7) and (8), we obtain t _d =1/1-k(T ₁ -kT ₁ ') (9). Here, the periods T ₁ and T ₁ ′ are T ₁ = t ₁ + t _d = C ₁ /i _C1 E + t _d (10) T ₁ ′ = t ₁ ′ + t _d = C ₁ /i _C1 E + t _d (11) . However, i _C1 and i _C2 are both constant flow values flowing through resistors R ₂ and R ₆ .

From equations (10) and (11), it is possible to measure the oscillation periods T ₁ and T ₁ ' when the selection signal A is at high level and low level, so by calculating equation (9), the delay time t _d can be measured. can be calculated.

Therefore, using equation (9), the capacitance C ₁ can be determined from equation (10) as C ₁ =i _C1 /E(T ₁ −t _d ) (10)'.

FIG. 4 is a block diagram showing the capacitance/time converter 11 when a differentially varying capacitor is used as the variable capacitor.

The output end of inverter G ₁ is NAND gate G ₃ , G ₄
, and each of its output terminals is connected to one terminal of each of the differential capacitances C _L and C _H as well as to each input terminal of the NAND gate G ₅ . The output end of NAND gate _G5 is connected to one end of anti- _R5 .

The other ends of the differential capacitances C _L and C _H are both connected to the common potential point COM via the capacitance C ₂ and are also connected to the non-inverting input terminal (+) of the operational amplifier Q ₁ . The output terminal of inverter _G1 is connected to the input terminal CL of n-bit counter CT via inverter _G6 , and its output terminal Qn is connected to the input terminal of NAND gate _G4 via inverter _G7 . Connected to the other input end of ₃ . Output V ₀ is obtained from the output end of inverter G ₇ .

Next, the operation of the capacitance/time converter 11 shown in FIG. 4 and configured as described above will be explained using the waveform diagram shown in FIG. 5.

First, when the selection signal A is at high level, the resistor
The case where R ₂ is selected will be explained. When the output terminal Qn of the counter CT is at a low level, _G3 is selected from among the NAND gates _G3 and _G4 , and the output terminal of _G4 is kept at a high level. Therefore, since NAND gates G ₃ and G ₅ each function as a simple inverter, NAND gate G ₃ has the same function as inverter G ₂ in FIG. 1, and the output terminal of NAND gate G ₅ is the same as the output terminal of inverter G ₁ . Make the same level change.

Therefore, when the output terminal Qn of the counter CT is at a low level, that is, during the period TL in FIG. 5C, the same operation as when the variable capacitor C ₁ in _FIG . do. Therefore, the voltage at the input terminal of operational amplifier Q ₁ is V ₁ ′, the voltage at the connection point of resistors R ₁ and R ₅ is V ₂ ′, and the voltage at the output terminal of operational amplifier Q _1.
V ₃ ' and the voltage V ₄ ' at the output terminal of the NAND gate G ₅ are the same as the voltages V ₁ to V ₄ in FIG. 1, respectively. As shown in FIG. 5B, the waveform of the voltage V ₁ ' at the non-inverting input terminal (+) of the operational amplifier Q ₁ with a period t _L is repeated by the number n of bits of the repetition counter CT.
Therefore, the period T _L of the output level of inverter _G7 corresponding to the low level of the output terminal of counter CT is (10)
In the same way as when we derived the formula, we get the following formula.

T _L =nt _L +nt _d =nC _L /i _C1 E+nt _d (12) However, i _C1 = R ₀ /R ₂ R ₅ |E/2|.

When the counter CT counts n pulses related to the differential capacitance _CL , the level of its output terminal Qn is inverted to high level. In this state, Nand Gate
Out of G ₃ and G ₄ , G ₄ is selected and the output terminal of G ₅ is kept at a high level. Therefore, Nandgate G ₃ ,
Each G ₅ acts as just an inverter,
NAND gate G ₄ is inverter G ₂ in Fig. 1
It has the same function as . Also, Nand Gate _G5
The output terminal of inverter _G5 has the same level change as the output terminal of inverter G5.

Therefore, when the output terminal Qn of the counter CT is at a high level, that is, during the T _H period in Figure 5 C, the operation is the same as when the variable capacitor C ₁ in Figure 1 is used as the differential capacitor C _H as the variable capacitor. do. Similarly to the case of the period T _H , the period T is T _H =nt _H +nt _d =nC _H /i _C1 E+nt _d (13).

Next, a case will be described in which the selection signal A is at a low level and anti- _R6 is selected. In this case, the operation is the same except that the selection signal A is at a high level and the oscillation period is different. Therefore, (12),
The periods T _L ′ and T _H ′ corresponding to equation (13) are T′ _L = nt′ _L + nt _d = nC _L /i _C2 E+nt _d (14) T′ _H = nt′ _H + nt _d = nC _H /i _C2 E+nt _d (15). However, i _C2 = R ₀ / ₆ R ₅ |E/2|.

In these cases, there is the relationship t _L = Kt′ _L (16) t _H = Kt′ _H (17), so using equations (12) to (17), the delay time t _d
is obtained as t _d =1/n・T _L −kT′ _L /1−k (18) t _d =1/n・T _H −kT′ _H /1−k (19).

Therefore, by measuring the oscillation frequencies T _L , T _H , T' _L , T' _H of the voltage V ₀ at the output terminal of the inverter G ₇ when the selection signal A is at high level and low level, the operational amplifier Q ₁ 's delay time t _d can be found. Therefore, using equation (18) or equation (19), the differential capacitance C _L ,
From equations (12) and (13), C _H is calculated as C _L = i _C1 / nE (T _H − nt _d ) (12)′ C _H = i _C1 / nE (T _L − nt _d ) (13)′ You can ask for it.

FIG. 6 is a block diagram showing the overall configuration according to the present invention.

12 is a microcomputer unit;
The output V ₀ of the capacity/time converter 11 is input.
The number of capacity/time converters may be 10, but here it is 1.
The explanation will be based on 1. 13 is a timer counter (T/D) that converts the time signal included in the output V ₀ into a digital value. 14 is RAM (random access memory), 15 is ROM (read only memory), and the addressing of these is
The data is transmitted from a CPU (processor) 16 via a bus 17 and a latch decoder 18. 19 is a data bus, and 20 is a control bus. The data taken in from the timer counter 13 is transferred to the data bus 1.
9 and stored in the RAM 14. ROM15
A predetermined calculation program and initial data are stored in the ROM 15 under the control of the CPU 16.
The result calculated according to the calculation procedure stored in
It is stored in RAM14. Further, the selection signal A is outputted to the capacity/time switching section 11 via the control bus 20 under the control of the CPU 16. The final calculation result is converted into a duty signal by the timer/counter 21, converted into an analog signal by the duty/analog converter 22, and then converted to an analog signal at the output terminal 23.
Output to. Timer/counter 21 and duty/
The analog converter 22 constitutes a digital/analog converter 24.

Next, the signal station of the embodiment shown in FIG. 6 will be explained using the flowchart shown in FIG.

First, the relationship between the differential capacitances C _L and C _H and the differential pressure ΔP will be explained. If the value of each differential capacitance C _L and C _H when the differential pressure ΔP is zero is C ₀ and the spring constant of the moving electrode 25 is K, then the differential capacitance C _L and C _H are as follows: C _L = C ₀ It can be expressed as 1/1-kΔP (20) C _H =C ₀ 1/1-kΔP (21). From these formulas, the differential pressure ΔP is calculated as ΔP=1/k(C _L −C _H /C _L +C _H ) (22).

The microcomputer unit 12 is operated in consideration of the above points. Prior to calculation, ROM
In step 15, the initial value _td0 of the delay time _td of the operational amplifier _Q1 is set as initial data, as shown in the step, and furthermore, in the step, the bit n of the counter necessary for the calculation, the coefficient k, and the constant current value i are stored in the RAM 14. _C1 ,
i _C2 , power supply voltage E, capacitance C ₀ when the differential pressure is zero, spring constant K, etc. are set.

In the above state, the output V ₀ (T _L , T _H ) from the capacity/time converter 11 under the control of the CPU 16
is read (step) and stored in the RAM 14. Using the stored data, the differential capacitance C _L ,
Calculate C _H (step) and store it in RAM 14. Since the delay time used in this case is the first calculation, the initial value _td0 set in step is used.

Next, in step, differential pressure calculation is executed using the calculation program shown in equation (22) stored in the ROM 15. The calculation result is output via the digital/analog converter 24.

Since the slew rate of operational amplifier Q ₁ does not change in a short time, the delay time _t d shown in equation (18) or (19) is shorter than the calculation cycle of differential pressure ΔP in equation (22).
The calculation may be performed and corrected in 1/5 to 1/10 cycles. Therefore, this correction cycle is determined in each step. If the predetermined correction cycle has not been reached, reading of the output V ₀ is repeated. When the predetermined correction period has been reached, the process moves to step and outputs the selection signal A to the capacitance/time converter 11 via the control bus 20, switches the switch SW to the resistor _R6 side, and outputs V ₀ (T' _H , T′ _LL ) is read into RAM14.
Store in. Next, in step, the calculation of equation (18) or (19) is executed according to the calculation procedure moved to ROM 14, and stored in RAM 14, and the process returns to step.

The calculations of C _L and C _H in the next step are executed using the delay time t _d calculated in the step. The same procedure is repeated below.

In addition, in the explanation so far, the constant current value flowing to the non-inverting input terminal (+) of operational amplifier Q ₁ was changed by changing the resistor, but this is not limited to this, and it is also possible to change the current value itself. Alternatively, the voltages V ₄ and V ₄ ', which are normally switched between E and zero, may be switched between (E- _ΔV ) and _ΔV for correction.

(Effects of the Invention) As described above in detail with the embodiments, according to the present invention, the charging/discharging current to the variable capacitor is changed at a fixed cycle or an arbitrary cycle, and the slew rate of the operational amplifier is calculated and corrected. I decided to do this, so
A highly accurate capacitive converter can be realized, and there is no need to use a high-speed operational amplifier.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a capacitance/time converter according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing waveforms of each part in FIG. 1, and FIG. 3 is a waveform diagram shown in FIG. 2. FIG. 4 is a block diagram showing another configuration of the capacity/time converter according to the embodiment of the present invention, and FIG.
6 is a block diagram showing the overall configuration of the present invention, and FIG. 7 is a waveform diagram showing the waveforms of each part in the figure.
FIG. 8 is a flow diagram explaining the signal processing in FIG. 8, and FIG. 8 is a block diagram showing the configuration of a conventional capacitive converter.
FIG. 9 is a waveform diagram showing waveforms at various parts in FIG. 8. 10, 11...Capacity/time converter, 12...Microcomputer unit, 13...Timer counter, 14...Random access memory, 15
...Read-only memory, 16...Processor,
19...Data bus, 20...Control bus, 24...Digital/analog converter, C ₁ ...
...variable capacitance, C _H , C _L ... differential capacitance, Q ₁ ... operational amplifier, A ... selection signal, CT ... counter.

Claims (1)

[Claims] 1 A variable capacitor whose capacitance changes according to the physical quantity to be detected, and an operational amplifier in which one end of the capacitor is connected to the non-inverting input terminal and a divided voltage of the output terminal voltage and a constant voltage is applied to the inverting input terminal. an inverter having an input terminal to which the output of the operational amplifier is applied, and applying a voltage at the output terminal to the other terminal of the variable capacitor in an inverted phase of the voltage through a logic element; a switching means that uses a switch to switch a constant current value to flow from a voltage division point with an output to a non-inverting input terminal of the operational amplifier; and a correction means that switches the switch in response to a selection signal to calculate and correct the slew rate of the operational amplifier. and computing means for computing the physical quantity from a frequency related to the output frequency of the inverter.