JPH0438529A - Information processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing apparatus, and relates to an apparatus for dynamically managing the operating environment of a central control unit of a multitasking system.

The operating environment of the central control unit refers to hardware constraints imposed on programs running on the CPU, such as operating speed, interrupt control, and address space. The present invention preferably relates to an apparatus for dynamic management of operating speed.

BACKGROUND ART] A central control unit (hereinafter referred to as a CPU) has been increasing its operating speed year by year, thereby dramatically increasing its processing capacity. However, some of the software executed there does not like the improvement in operating speed. This includes so-called game software and software timers. Additionally, there are some memories and external devices that cannot keep up with the increase in CPU operating speed.

The electronic computer 400 shown in FIG. 4 is inputted with an IMHz clock, and the operating speed of the CPU 401 is constant for any instruction, and the number of instructions processed per second is one million (hereinafter referred to as IMHz).
Mips). Also, the device 403 is an input/output device that also responds to instructions from the CPU 401.
It is assumed that synchronous operation is possible at MHz.

The computer 400 has IMi no matter which program it executes.
It can be executed with ps.

By the way, if it is assumed that the operating speed of the CPU 401 inside the computer 400 has been improved to 2 MHz, its processing capacity will naturally be 2M1 ps.

However, the program that attempts to use the device 403 cannot run at the operating speed of the device 403, which is not 2MHz.
It cannot be executed as is.

FIG. 5 shows C-P of the electronic computer 400 shown in FIG.
The U 401 is replaced by a CPU 501 that can operate even at 2MH2. Also. The clock generator 504 has an additional circuit that selects the IMH2 clock and 2 MHz clock based on the external switch 508 from the clock obtained from the oscillator 505 and transmits it to the CPU 501. The device 503 only operates at 1 MHz, which is the same as the device 403. shall not be possible.

As a result, a program that does not use the device 503 can achieve twice the performance as compared to when it is executed on the computer 400. In addition, the IMH
By simply selecting the clock of z, it is possible to perform the same operation as the electronic computer 400, and it is possible to inherit the assets of the device 503 itself and the software that uses it.

FIG. 6 schematically shows the number of steps and the execution time of a program that runs on the computer 500. It is assumed that the program 600 is divided into four tasks 601 to 604. For convenience of explanation, tasks 601 to 604
are composed of the same number of steps, and the execution time of each when executed by IMips is all T, which is the same.

Furthermore, it is assumed that the task 601 is an initial program and the task 603 is an arithmetic program that does not access the low-speed device 503. Further, it is assumed that task 602 is a program for obtaining input from the operator, and task 604 is an output program for the operator, and that each uses the device 503, and that they are executed in order from 601 to 602, 603, and 604.

Therefore, tasks 601 and 603 can normally operate on the CPU 501 with a capacity of 2M1 ps, and tasks 602 and 604 can only operate with IMipS.

Here, the program 600 is converted to IMips on the computer 500.
When executed, the execution time 610 can be expressed as the sum of 4T of the execution times 611 to 614 of each task. For convenience of explanation, the size is shown in FIG. 6 as the same size as the number of steps in the program.

Change the switch 506 of the computer 500 to select the 2MH2 clock, and increase the performance of the CPU 501 to 2M1.
Assume that the program 600 is executed after setting the value to pB.

The task 601 operates at 2M1 ps as assumed, and its operating time 621 ends at T/2. However, task 602
cannot operate at 2M1ps because it executes a low-speed device 503. Therefore, the program 600 encounters a failure at this point and is interrupted.

[Problems to be Solved by the Invention] In the prior art, the operating speed of the CPU must be determined each time according to the slowest peripheral device (including memory and operator operating environment) used by a certain program. Furthermore, each user must always be aware of the operating environment of the program he/she intends to use.

Also, the overall efficiency of the program cannot benefit from the increased operating speed of CPtJ unless the peripherals are improved. In some cases, it may be necessary to rebuild parts or all of them.

[Means for Solving the Problems] The present invention includes a central control unit, a register unit that can determine the operating environment of the central control unit, and a register unit that allows the central control unit to directly write to the register unit. When the central control unit attempts to start execution of one job from the queue of jobs to be executed, information on the operating environment of the central control unit unique to the job is stored in the register. and means for specifying an operating environment of the central control section when the job to be executed does not specify the register section. The invention is characterized in that it is equipped with an external switch means.

[Embodiment] FIG. 1 shows an electronic computer 100 shown in claim 1, which is almost the same as the electronic computer 500 described in the prior art section, except that the switch 506 is replaced by a register 106 and its writing means 107. have.

The contents written in the register 106 are sent to the clock generator 104.
The clock to be transmitted to the CPU 100 can be determined.

Also, the register 106 is written from the CPUl0I to the writing means 1.
It is possible to rewrite at any timing via the CPU 07, thereby allowing the CPU 10I to set its own operating speed by itself.

FIG. 2 schematically shows the number of steps of a program that runs on the computer 100, and has the same configuration as the program 600 described in FIG. 6. Program 20
0 is divided into four tasks 201 to 204,
And the same size from 201 to 202.203.204
It shall be executed in order.

However, it is assumed that each task has at the beginning information specifying its own operating speed and instructions 221 to 224 to be written to the register 106 shown in FIG.

Similarly to FIG. 6, it is assumed that task 201 is an initial program, task 203 is an arithmetic program, and that each of tasks 201 and 203 does not use the low-speed device 103. Further, it is assumed that task 202 is a program for obtaining input from the operator, task 204 is a program for outputting to the operator, and that each of the tasks 202 and 204 uses the device 103.

Now, when the program 200 starts operating on the computer 100, the task 201 is called first. At the beginning of the task 201 there is an instruction 221 for setting the operating speed of the CPU I0I to 2MHz,
Information is written to register 106 via 7. Therefore, the CPU 101 executes the task 201 with a capacity of 2M1 ps, and the execution time can be expressed as 211 in FIG. 2. Compared to this, it takes half the time T/2.

Next, when the task 202 is called, the clock of the CPU101 executes the instruction 222, and the operating speed of the CPU is set to IM.
Hz and CPU10I is executed at IMips. As a result, the execution time 212 of task 202 is the same as the execution time 612 of one hour required by task 602 in FIG.

In the same way, the task 203 returns to 2MH by instruction 223.
z clock is selected and its execution time 213 is 61
The time is T/2, which is half of 3, and the instruction 22 of task 204
4 selects the IMHz clock and its execution time 21
4 is the same as 614, which is one hour.

Execution time 212.214 of input/output tasks 202 and 204
Since the operating speed is the same as that of a conventional computer, the operator will be able to use it in the same way as a conventional electronic computer. Furthermore, the execution time 213 of the task 203, which is the operator's actual waiting time, is T/2, which is half the amount of CPU performance improvement.
It's time. The total operating time 210 becomes 3T hours due to the effect of increasing the operating speed, which makes it possible to improve performance by 25% compared to 4T hours of the conventional technology.

The conventional execution time is shown at 611 on the left side of Figure 2 for comparison.
．． 612.613.614.

Furthermore, the user can improve the operating efficiency of the CPU without being aware of the operating speed or setting switches, and the interruption of the program due to incorrect selection of the operating speed as described in the prior art section does not occur.

By the way, since programs and tasks do not necessarily have a specific execution speed, the first claim
The information specified in the register shown in section may become undefined. In this case, it is preferable to provide a switch that allows the operator to directly set the operating speed of the CPU, as in the electronic computer 500 shown in the prior art.

FIG. 3 shows an electronic computer 300 in which an auxiliary circuit means shown in claim 2 is added to the electronic computer 100. The contents of the register 306 of the computer 100 and the contents of the switch 308 are transferred to the R-S flip-flop 3.
The register/switch selection circuit makes a selection depending on the output state of 09. This allows the operating speed of the CPU 301 to be specified by both the CPU 301 itself and the switch 308.

The output of the R-S flip-flop 309 is initially set to L, and the register/switch selection circuit 310 selects the switch 308. At this time, the operating speed of the CPU 300 can be specified by the operator via the switch 308.

Thereafter, when writing to the register 306 is performed as in the previous example and in the embodiment, the output of the R-S flip-flop 309 becomes H, and the register/switch selection circuit 310 selects the contents of the register 306. It is transmitted to the clock selection circuit 304 corresponding to 1°4.

[Effects of the Invention] In particular, an increase in the operating speed of the CPU increases the operating efficiency of the entire system. However, in commercializing the product, it is difficult to simultaneously match the operating speeds of peripheral devices. In the conventional technology, some software cannot take advantage of the increased efficiency of the CPU due to the influence of some peripheral devices.

By dynamically changing the operating environment of the CPU in response to increased CPU speed, the present invention enables efficient operation and inheritance of conventional assets without the operator being aware of it.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an information processing apparatus according to the present invention. FIG. 2 is a schematic diagram showing a program that operates according to the present invention and its execution time. FIG. 3 is a schematic diagram showing an information processing device further comprising an auxiliary circuit according to the present invention. FIG. 4 is a diagram showing a conventional electronic computer. FIG. 5 is a diagram showing an electronic computer partially modified according to the prior art. FIG. 6 is a schematic diagram showing a program executed by the electronic computer of FIG. 5 and its execution time according to the prior art. 101, 301: cpu 102.302: memory and peripherals 103.303
:Low speed device 104.304: CPU clock selection circuit 105.3
05: Oscillator 106.306: Clock selection register 107.307
:Write circuit 308: Switch 309: 310: 120. 201: 202: 203: 204: R-S flip-flop register/switch selection circuit 320: Common path task 1, initial program task 2, input program task 3, arithmetic program task 4, output program and above

Claims (2)

[Claims] (1) A central control unit, a register unit that can determine the operating environment of the central control unit, circuit means that allows the central control unit to directly write to the register unit, and means for writing information on the operating environment of the central control unit unique to the job to the register unit when attempting to start execution of one job from a queue of jobs to be executed; An information processing device comprising: (2) If the job to be executed does not specify the register section, an external switch means is provided for specifying the operating environment of the central control section. information processing equipment.