JPH0438541A - Digital signal processor - Google Patents

Abstract

PURPOSE:To improve the versatility of the digital signal processor by dividing a data memory into a sample processing part and a block processing part. CONSTITUTION:In the digital signal processor, a data memory 5 is divided into two parts. One part is used for a sample processing and the other is used for a block processing. A sample processing part 5a increments a base address counter 1 synchronizing with a sampling cycle, and a block processing part 5b increments a base address counter 2 synchronizing with a block cycle. When a signal processing is enough for each sample, the above-mentioned block processing part 5b is used as the sample processing part as well, and the entire data memory 5 is used as the sample processing part. By using the increment type address counters 1 and 2 for memory access to the data memory 5, correspondence can be made to both the signal processing for each sample and the signal processing for each block.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing device that performs arithmetic processing on a supplied digital signal.

[Summary of the invention]

The present invention provides a digital signal processing device that performs arithmetic operations on a supplied digital signal, including a sample processing unit that performs arithmetic processing on a sample-by-sample basis on a data memory provided within the digital signal processing device; The sample processing section increments the base address in synchronization with the sampling period, and the block processing section increments the base address in synchronization with the block period. By incrementing , or by connecting the above block processing section as a sample processing section when only processing the supplied digital signal in units of samples, and using the entire data memory as a sample processing section. and, by using an increment type address counter for memory access to the data memory, it is a digital signal processing device that can easily perform arithmetic processing on a sample-by-sample or block-by-block basis depending on the processing content. .

[Prior Art] In arithmetic processing using a so-called DSP, which is a digital signal processing device, signal processing is required both for each sample of a supplied digital signal and for each block of a predetermined plurality of samples. There are cases.

For example, in order to reduce the recording density and transmission rate, a bit compression device that processes a predetermined number of samples of the supplied digital signal as one block and performs bit compression processing for each block is used by the DSP. For example, it may be realized by software.

Various types of bit compression devices for each block have been considered, one example of which is the bit compression device shown in FIG.

The bit compression device shown in FIG. 4 also requires sample-by-sample and block-by-block processing of the supplied digital signal. First, the analog signal from the input terminal 51 is sampled at a predetermined frequency. A sample-by-sample digital signal is provided after analog-to-digital conversion.

The digital signal supplied for each sample is supplied to a zero-order (straight) filter 52, a first-order filter 53, and a second-order filter 54, respectively.

The zero-order filter 52 outputs the supplied digital signal for each sample as it is, and supplies this to the intra-block maximum absolute value detection circuit 55.

The first-order filter 53 calculates the difference between the current sample data of the supplied digital signal for each sample and the sample data immediately before the current sample data, and calculates the difference between the maximum absolute value detection circuit 56 in the block. supply to.

The secondary filter 54 calculates the difference between the current sample data of the supplied digital signal for each sample and the sample data two times before the current sample data, and supplies this to the intra-block maximum absolute value detection circuit 57. do.

The intra-block maximum absolute value detection circuits 55, 56 and 57 detect the maximum absolute value within the block for each block, with a predetermined plurality of samples of the digital signal supplied for each sample as one block, and detect the maximum absolute value within each block. It is supplied to the comparison range detection circuit 58.

The comparison range detection circuit 58 selects filter data from the selector 5 indicating which filter the digital data with the minimum value has passed through among the maximum absolute values within the three blocks supplied.
9 and output terminal 64, the range of the digital data of the minimum value is detected, and this is supplied as range data to ranging circuit 61 in block floating processing section 60 and output terminal 65.

The selector 59 selects the digital signal of the block passed through the filter specified by the filter data and supplies it to the ranging circuit 61 .

The ranging circuit 61 shifts the supplied digital signal for each block based on the range data and supplies it to the requantizer 62 .

The requantizer 62 requantizes the block-by-block digital signal shifted based on the range data into predetermined bits, and outputs it as encoded data via the output terminal 63.

Note that this encoded data is decoded based on the filter data outputted via the output terminal 64 and the range data outputted via the output terminal 65.

Here, there are various types of address access, but if the above filter calculation is performed using the address access using increment, the digital signal supplied for each sample is temporarily stored in a memory etc., and then stored at a predetermined address. Filter calculations such as obtaining the above-mentioned first-order difference and second-order difference are performed based on the sample data. When the filter calculation for one sample is completed, the address is incremented by 1 and the filter calculation is performed again based on the next sample data. Calculations are made.

On the other hand, in order to detect the maximum value within a block, for example, one block of digital signals is sequentially supplied to the data memory for each sample, and the currently stored digital data is larger than the digital data supplied later. It is detected by rewriting only when it is large.

[Problem to be solved by the invention]

However, when detecting the maximum value within the block, it is more convenient not to increment the address for each sample as in the filter calculation for each sample.

In addition, even when signal processing is required for each sample and each block, as with the bit compression device described above, the base address can be incremented according to the signal processing content, making it easy to perform digital signal processing. Development of a device is desired.

The present invention has been made in view of the above-mentioned problems, and provides a digital signal processing device that has a simple configuration and can facilitate signal processing by incrementing a base address according to the processing content of the signal. purpose.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present invention provides a digital signal processing device that performs calculations on a supplied digital signal, in which a data memo IJ in the digital signal processing device is stored as a data memo for each sample of the supplied digital signal. The data is divided into a sample processing section for performing arithmetic processing on a sample-by-sample basis, and a block processing section for performing arithmetic processing on a block-by-block basis, with a predetermined plurality of samples of the supplied digital signal as one block. The processing section increments the base address in synchronization with the sampling period, and the block processing section increments the base address in synchronization with the block period.
In addition, when performing only sample-by-sample processing on the supplied digital signal, the block processing section is also connected as a sample processing section, and the entire data memory is used as the sample processing section. An increment type address counter is used for memory access to data memory.

[Function] In the digital signal processing device according to the present invention, the data memory is divided and one part is used for sample processing and the other part is used for block processing, and the sample processing section increments the base address in synchronization with the sampling period. ,
The block processing section increments the base address in synchronization with the block period, and when signal processing only needs to be performed for each sample, the block processing section also serves as a sample processing section, and the entire data memory is sampled. By using an increment type address counter for memory access to the data memory, it is possible to support both sample-by-sample signal processing and block-by-block signal processing.

〔Example〕

Embodiments of the digital signal processing device according to the present invention will be described below with reference to the drawings.

As shown in the functional block diagram of FIG. 1, the digital signal processing device according to the present invention includes a first address counter 1 that increments a base address for each sample of the supplied digital signal; A second address counter 2 that takes multiple samples as one block and increments the base address for each block.
a selector 3 that selects and outputs the base address from the first address counter 1 or the base address from the second address counter 2 according to the processing content of the signal; and a logical address supplied from the input terminal 6. and the base address selected from the selector 4, and supplies the result to the data memory 5 as a physical address.
and a data memory 5, such as a RAM (Random Access Memory), whose storage area is divided into a sample processing section 5a and a block processing section 5b.

An example of the operation of the digital signal processing apparatus having such a configuration when the data memory 5 is used in a divided manner is shown in the flowchart of FIG.

In this example, the read address from the data memory 5 is controlled according to the sign of the MSB (most significant bit) of the logical address supplied from the input terminal 6.

First, in step 10, it is determined whether or not the MSB of the logical address supplied from the input terminal 6 is "O". If YES, the process proceeds to step 11; if NO, the process proceeds to step 12.

This logical address is output according to the signal processing content,
For example, when the signal processing is performed on a sample-by-sample basis, a logical address with the MSB set to "0" is supplied to the adder 4 via the input terminal 6, and when the signal processing is performed on a block-by-block basis, M
A logical address with SB set to "1" is supplied to the adder 4 via the input terminal 6.

In step 11, the MS of the supplied logical address is
When B is 10', the selector 3 selects the base address from the first address counter 1 that increments the base address for each sample, since signal processing for each sample is desired, and the process proceeds to step 13.

The base address from this first address counter 1 is supplied to an adder 4.

In step 13, in the adder 4, the MSB is “
The logical address of "0" and the base address from the first address counter l are added, and the MsB obtains a physical address of "01" and proceeds to step 15.

In step 15, the physical address of this MSB "@0" is supplied to the data memory 5 and the process ends.

That is, when the MSB of the logical address is 0'', when the base address supplied from the selector 3 is added by the adder 4, it indicates the address of the sample processing unit 5a, and this MSB is 0. By supplying the physical address of " to the data memory 5, signal processing can be performed on the data stored in the sample processing section of the data memory.

On the other hand, if it is determined in step 10 that the MSB of the logical address is not "O" but "1", step 1
At step 2, the selector 3 selects the base address from the second address counter 2 and proceeds to step 14.

This indicates that when the MSB of the logical address is "1", the signal processing stored in the block processing unit 5b is performed, so the selector 3 inputs the address data for each block of the supplied digital signal. The base address from the second address counter 2 which is being incremented is selected and supplied to the adder 4.

In step 14, in the adder 4, the MSB is “
1 degree logical address and the second address counter 2
Add the base address of each block from
obtains the physical address of "BI" and proceeds to step 15.

In step 15, the physical address generated by the adder 2 is supplied to the data memory 5, and the process ends.

Since the MSB of this physical address is '1', signal processing is performed on the digital signal stored in the block processing section 5b in the data memory 5.

In this way, the first address counter 1 increments the base address for each sample of the supplied digital signal, and the second address counter 2 increments the base address for each block of the digital signal, and the signal processing A logical address corresponding to the content is supplied to the adder 4, and a base address from the first address counter 1 or the second address counter 2 is selected according to the signal processing content, and the adder 4 inputs the above logic address. By applying power to the address and the selected base address to make it a physical address, and performing signal processing of the digital signal stored in the data memory using this physical address, each sample or block of the digital signal is processed according to the signal processing content. It is possible to perform signal processing for each signal.

Therefore, it is easy to handle cases where the first half of the circuit requires signal processing for each sample, and the second half of the circuit requires signal processing for each block, such as the above-mentioned bit compression device. I can do it.

In the above embodiment, the case where the increment of the base address is switched for each sample and the increment of the base address for each block is explained. If a program is designed to perform another filtering process or the like when an interrupt occurs, the base address may be incremented only when this interrupt occurs.

In this case, the data memory 5 may be divided into a sample processing section and an interrupt processing section, and the sample processing section increments the base address for each sample, and the interrupt processing section increments the base address each time an interrupt occurs.

Further, in the digital signal processing device according to this embodiment, the entire divided data memory can be used only as a sample processing section.

In this case, as shown in the flowchart for non-division in FIG. 3, first, in step 20, the selector 3
The base address is selected from the first address counter 1, which increments the base address for each sample of the supplied digital signal, and the process proceeds to step 21.

The data memory 5 unifies the divided storage areas and converts the entire storage area into only a sample processing section in accordance with the supplied digital signal.

Therefore, in step 21, the base address supplied from the first address counter 1 is supplied as is to the data memory 5, and the process ends.

The digital signal stored in the data memory 5 is processed sample by sample according to this base address.

Note that the second address counter may also increment the base address for each sample, and the selector 3 may select the base address from the first or second address counter 1.2.

In this way, the data memo IJ 5 that was divided and used
By using the entire storage area only for the sample processing section, it is possible to perform arithmetic processing such as filter calculation of twice the order than when using the above-mentioned division.

〔Effect of the invention〕

The digital signal processing device according to the present invention divides the data memory in the digital signal processing device into a sample processing section and a block processing section, and performs data access to the data memory according to the sampling period of the supplied digital signal. By selecting and using the base address from an address counter that synchronously increments the base address or the base address from an address counter that increments the base address synchronously with the block period of the digital signal, the signal processing contents can be adjusted. Sample-by-sample or block-by-block signal processing can be performed accordingly.

Therefore, the versatility of the digital signal processing device can be increased, such as focus compression encoding/decoding and N
The present invention can easily be applied to devices that require block processing in addition to sample processing, such as signal processing such as AT-based speech recognition.

Furthermore, by using the entire data memory as a sample processing section, it is possible to perform arithmetic processing of twice the order as compared to when the division is used.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of the digital signal processing device according to the present invention, FIG. 2 is a flowchart for explaining the operation when using the divided data memory of the embodiment, and FIG. 3 is a block diagram of the data memory of the embodiment. It is a flowchart for explaining the operation during use. FIG. 4 is a functional block diagram of the bit compression device. 3・・・・・・・・・・・・Selector 4・・・・・・・・・Adder

Claims (3)

[Claims] (1) In a digital signal processing device that performs calculations on a supplied digital signal, the data memory in the digital signal processing device is used to perform calculation processing on a sample basis for each sample data of the supplied digital signal. The sample processing section is divided into a sample processing section and a block processing section for processing a predetermined plurality of samples of the supplied digital signal as one block and performing arithmetic processing for each block. , and the block processing unit increments a base address in synchronization with a block period. (2) When processing the supplied digital signal only in units of samples, the block processing section is also connected as a sample processing section, and the entire data memory is used as the sample processing section. Claim (1
) described digital signal processing device. (3) The digital signal processing device according to claim (1), wherein an increment type address counter is used for memory access to the data memory.