JPH0438827A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0438827A
JPH0438827A JP14572490A JP14572490A JPH0438827A JP H0438827 A JPH0438827 A JP H0438827A JP 14572490 A JP14572490 A JP 14572490A JP 14572490 A JP14572490 A JP 14572490A JP H0438827 A JPH0438827 A JP H0438827A
Authority
JP
Japan
Prior art keywords
film
resist
patterning
dry etching
etching method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14572490A
Other languages
Japanese (ja)
Inventor
Michio Sakurai
櫻井 道雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP14572490A priority Critical patent/JPH0438827A/en
Publication of JPH0438827A publication Critical patent/JPH0438827A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent dropout of resist in a photolithography step by sequentially forming an Al or Al alloy film, a tungsten silicide film, and an Si film on a semiconductor substrate through an insulating film, patterning them by using a mask of a photoresist film by an anisotropically dry etching method, and then removing the retaining Si film. CONSTITUTION:After an SiO2 film is formed on an Si substrate 6, an Al film 4, a WSix film 3, an Si film 2 are continuously formed, further coated with photoresist 1, and the resist is then patterned. In this case, since the film 2 and the resist 1 have high bonding strength, the dropout of the resist does not occur. Then, with the resist 1 after patterning as a mask the film 4, the film 3 and the film 2 are anisotropically dry etched, wired, and the resist 1 is then removed. Thereafter, the film 2 is removed by an anisotropically dry etching method.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に電極配線の
形成法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming electrode wiring.

〔従来の技術〕[Conventional technology]

従来、半導体装置の製造工程における電極配線の形成は
、電極配線材料にAlあるいはAJ合金薄膜を単層で形
成してきたが、最近の素子の集積化に伴ない配線幅が小
さくなるにつれ、エレクトロマイグレーションやストレ
スマイグレーションなどの深刻な信頼性上の障害が生じ
ている。エレクトロマイグレーションの解決策の1つと
してはAJあるいはAI合合金膜膜上タングステンシリ
サイド(以下WSixと記す)薄膜を形成した積層構造
の配線が提案されている。しかし従来は前記積層構造の
配線をバターニングすることは次に示す理由から困難で
あった。
Conventionally, electrode wiring has been formed in the manufacturing process of semiconductor devices by forming a single layer of Al or AJ alloy thin film as the electrode wiring material, but as the wiring width becomes smaller due to recent integration of devices, electromigration Serious reliability failures such as stress migration have occurred. As one solution to electromigration, a layered wiring structure in which a tungsten silicide (hereinafter referred to as WSix) thin film is formed on an AJ or AI alloy film has been proposed. However, conventionally, it has been difficult to pattern the wiring in the laminated structure for the following reasons.

つまりAlあるいはAρ合合金膜膜上形成したWSix
薄膜は、フォトリソグラブイーにおいてレジスト欠落を
発生し易い、このレジスト欠落とは第2図(a)に示す
ように、UV光11でウェハー14上のレジスト12を
露光する時に、レジスト中の感光剤であるナフトキノン
ジアジドがインデンカルボン酸に分解してN2ガス13
を発生する。このため第2図(b)に示すように、レジ
ストと基板の接触強度が低い場合に、発生したN2ガス
13がレジスト−基板界面に進入して、レジストを基板
より剥離する。その結果第2図(C)に示すように、現
像後にレジストが欠は落ち欠落部15が発生する現象で
あると考えられる。したがってレジスト欠落と基板の種
類とは密接な関係があり、特にA(あるいはA(合金薄
膜上に形成したW S i y、薄膜は最もレジスト欠
落を発生し易い基板の1つであると考えられている。
In other words, WSix formed on Al or Aρ alloy film
Thin films are prone to resist missing in photolithography. This resist missing occurs when the resist 12 on the wafer 14 is exposed to UV light 11, as shown in FIG. Naphthoquinonediazide decomposes into indene carboxylic acid and generates N2 gas 13
occurs. Therefore, as shown in FIG. 2(b), when the contact strength between the resist and the substrate is low, the generated N2 gas 13 enters the resist-substrate interface and peels the resist from the substrate. As a result, as shown in FIG. 2(C), it is thought that this is a phenomenon in which the resist falls off after development and a missing portion 15 is generated. Therefore, there is a close relationship between resist chipping and the type of substrate, and in particular, thin films formed on A (or A) alloy thin films are considered to be one of the substrates most likely to cause resist chipping. ing.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置の製造工程における電極配線
の形成方法では、エレクトロマイグレーションやストレ
スマイグレーションが生じるという問題点がある。また
、AlあるいはA!;!合金薄膜上にWSix薄膜を形
成した積層構造のtIgi配線を形成する場合も、フォ
トリゾグラフィーによりレジスト欠落を発生し易いとい
う問題点があった。
The conventional method of forming electrode wiring in the manufacturing process of a semiconductor device described above has a problem in that electromigration and stress migration occur. Also, Al or A! ;! Even when forming a tIgi wiring having a laminated structure in which a WSix thin film is formed on an alloy thin film, there is a problem in that resist chipping is likely to occur due to photolithography.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、半導体基板上に絶縁
膜を介してA(またはA(合金膜とタングステンシリサ
イド膜と5iWi!とを順次形成する工程と、フォトレ
ジスト膜からなるマスクを用い異方性ドライエツチング
法により前記Si膜とタングステンシリサイド膜とAρ
またはAl合金膜とをパターニングする工程と、パター
ニング後桟されたSi膜を異方性ドライエツチング法に
より除去する工程とを含んで構成される。
The method for manufacturing a semiconductor device of the present invention includes a step of sequentially forming A (or A (alloy film, tungsten silicide film, and 5iWi!) on a semiconductor substrate via an insulating film, and using a mask made of a photoresist film. The Si film, tungsten silicide film and Aρ
Alternatively, the method includes a step of patterning an Al alloy film, and a step of removing the exposed Si film after patterning by an anisotropic dry etching method.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を説明するための半導体チッ
プの断面図である。
FIG. 1 is a sectional view of a semiconductor chip for explaining one embodiment of the present invention.

まず第1図(a)に示すように、Si基板6の上にSi
○2膜5を熱酸化により形成後、スパッタ装置でパワー
5kW、圧力15mTorr、形成温度200℃の条件
で1.0μmのAρ膜4と500人のW S i x膜
3と500人のSi膜2を連続に形成し、さらにフォト
レジスト1を塗布する。次に第1図(b)に示すように
、フォトリソグラフィー技術を用いてレジストのパター
ニングを行う。このとき、Sig!2とレジスト1は接
着強度が高いためレジスト欠落は発生しない。
First, as shown in FIG. 1(a), Si
○After forming two films 5 by thermal oxidation, a 1.0 μm Aρ film 4, a 500-layer W Si x film 3, and a 500-layer Si film were formed using a sputtering device under the conditions of a power of 5 kW, a pressure of 15 mTorr, and a formation temperature of 200°C. 2 is continuously formed, and then photoresist 1 is applied. Next, as shown in FIG. 1(b), the resist is patterned using photolithography technology. At this time, Sig! Resist No. 2 and Resist No. 1 have high adhesive strength, so no resist dropout occurs.

次に第1図(c)に示すように、パターニング後のレジ
スト1をマスクとして、Aρ膜4とWSi x g! 
3とS1膜2をCρ系のガスにF系のガスを混合し80
0W、10Paの条件で異方性のドライエツチングをし
て配線の加工行う0次に第1図(d)に示すように、有
機溶剤を主成分とした剥離剤でレジスト1の除去を行う
0次に第1図(e)に示すように、Si膜2を800W
、10Paの条件でF系のガスを用いた異方性ドライエ
ツチング法で除去する。
Next, as shown in FIG. 1(c), using the patterned resist 1 as a mask, the Aρ film 4 and WSi x g!
3 and S1 film 2 by mixing Cρ-based gas and F-based gas at 80°C.
The wiring is processed by anisotropic dry etching under the conditions of 0 W and 10 Pa. Next, as shown in FIG. 1(d), the resist 1 is removed using a stripping agent mainly composed of an organic solvent. Next, as shown in FIG. 1(e), the Si film 2 was heated at 800 W.
, 10 Pa using an anisotropic dry etching method using F-based gas.

上記実施例ではスパッタ法でSi膜2を形成していたが
、プラズマCVD法でS i M 2を形成しても同様
の欠落防止効果が得られる。なお、プラズマCVD法に
よるS1膜の形成条件は、原料ガスがSiH4,成長圧
力が0.1Torr、成長温度が300″C,PRFワ
ーが1kWである。またこの5iJliの厚さは200
人以上であれば欠落防止の効果がある。
In the above embodiment, the Si film 2 was formed by sputtering, but the same chipping prevention effect can be obtained by forming SiM 2 by plasma CVD. The conditions for forming the S1 film by the plasma CVD method are as follows: source gas is SiH4, growth pressure is 0.1 Torr, growth temperature is 300''C, and PRF power is 1kW.The thickness of this 5iJli is 200mm.
If it is more than one person, it has the effect of preventing omissions.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、AlあるいはA、&合金
膜上にW S i x膜を形成した積層構造の半導体装
置用の電極配線を形成する工程において、WSiX膜上
にSi膜を形成する工程を加えることにより、フォトリ
ソグラフィー工程においてレジスト欠落を防止できると
いう効果を有する。
As explained above, the present invention involves forming an Si film on a WSiX film in the process of forming an electrode wiring for a semiconductor device having a stacked structure in which a WSi x film is formed on an Al, A, & alloy film. The addition of this step has the effect of preventing resist chipping in the photolithography process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を説明するための半導体チッ
プの断面図、第2図はレジスト欠落を説明するための半
導体チップの断面図である。 1・・・レジスト、2・・・Si膜、3・・・WSix
M、4・・Aρ膜、5・・SiO2膜、6・・・S1基
板、11・・・U■光、12・・レジスト、13・・・
N2ガス、14・・・ウェハー、15・・欠落部。
FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor chip for explaining resist missing. 1...Resist, 2...Si film, 3...WSix
M, 4...Aρ film, 5...SiO2 film, 6...S1 substrate, 11...U■ light, 12...resist, 13...
N2 gas, 14... wafer, 15... missing part.

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上に絶縁膜を介してAlまたはAl合金膜
とタングステンシリサイド膜とSi膜とを順次形成する
工程と、フォトレジスト膜からなるマスクを用い異方性
ドライエッチング法により前記Si膜とタングステンシ
リサイド膜とAlまたはAl合金膜とをパターニングす
る工程と、パターニング後残されたSi膜を異方性ドラ
イエッチング法により除去する工程とを含むことを特徴
とする半導体装置の製造方法。
A step of sequentially forming an Al or Al alloy film, a tungsten silicide film, and a Si film on a semiconductor substrate via an insulating film, and then forming the Si film and tungsten silicide by an anisotropic dry etching method using a mask made of a photoresist film. A method for manufacturing a semiconductor device, comprising the steps of patterning a film and an Al or Al alloy film, and removing a Si film left after patterning by an anisotropic dry etching method.
JP14572490A 1990-06-04 1990-06-04 Manufacture of semiconductor device Pending JPH0438827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14572490A JPH0438827A (en) 1990-06-04 1990-06-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14572490A JPH0438827A (en) 1990-06-04 1990-06-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0438827A true JPH0438827A (en) 1992-02-10

Family

ID=15391668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14572490A Pending JPH0438827A (en) 1990-06-04 1990-06-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0438827A (en)

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