JPH043943A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device using InAs having high electron mobility as an active layer having excellent crystallinity by altering the GaAs composition ratio (x) of a GaxIn1-xAs buffer layer approximately linearly from 0.47 where the buffer layer is in lattice-matching with InP to 0 and bringing the rate of change to 1.5X10<-3>/nm or less. CONSTITUTION:A non-dopted GaxIn1-xAs buffer layer 5 is formed onto a semi- insulating InP substrate 4 so that a GaAs composition ratio (x) reduces approximately linearly to film thickness, the (x) is brought to 0.47 lattice-matching with InP on the interface with the semi-insulating InP substrate 4, is decreased gradually toward the surface side and is brought to 0 finally, and a non-doped InAs active layer 6 is formed while the rate of change of the GaAs composition ratio (x) is 1.5X10<-3>/nm or less. When growth is conducted through a molecular- beam epitaxial growth method, the growth temperature of the non-doped GaxIn1-xAs buffer layer 5 is 450 deg.C and that of the non-doped InAs active layer 6, 400 deg.C, thus growing InAs having excellent surface homology without damaging the superior electrical characteristics of InAs. Accordingly, the lowering of the electron mobility of the InAs active layer and the deterioration of surface morphology can be inhibited extremely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device and a method for manufacturing the same.

[Prior Art] At present, high electron mobility transistors (HEMTs), including GaAs MES FETs, use high-mobility two-dimensional electron gas formed at the heterojunction interface between n-type A E GaAs and non-doped GaAs. Ya, non-dope A
Various devices using a GaAs layer as a channel have been developed, such as a beta-junction MIS structure FET using a semiconductor layer such as an fGaAs layer as an insulating layer, and are applied to high-speed switching elements, microwave elements, and the like.

In recent years, GaXIn1-x As, which has a higher electron saturation velocity than GaAs, has been used as an alternative material to GaAs.
has been attracting attention, and research on devices using this GaMIn+-x As for channels is being actively conducted.

Ga, In, and □As can be changed from GaAs to InAs by changing the Inlls composition ratio, and physical constants such as lattice constant and energy band gap can be changed continuously. However, in practice, there is a problem of the difference in lattice constant with the substrate used, so Gao, n7Ino, and 53AS, which are lattice-matched to the InP substrate, are used, and A f o, asTno, and 53AS, which are lattice-matched to InP, are used.
A structure in which a heterojunction is formed with 5zAs, and a heterostructure having three layers of strained 1 nGa thin enough that the film thickness does not exceed the critical film thickness determined by the difference in lattice constant with the substrate are widely used.

On the other hand, InAs has an electron mobility of 3.3X10' at room temperature.
It exhibits high mobility reaching up to cm''/V・S, and is expected to improve the performance of electronic devices.The only substrate that can lattice match with InAs is an InAs substrate, but InAs on an InAs-based substrate has a high mobility of 77%. The electron mobility of 10'cm''
/■•S was obtained.

Further, since the occurrence of crystal defects due to lattice mismatch cannot be avoided, attempts have been made to reduce the defect density in the InAs layer by using a superlattice buffer on a GaAs substrate.

Figure 3 shows an I formed on a GaAs substrate by the above method.
A heterostructure of nAs is shown. Ino, eGao, zAs and GaAs are alternately deposited on a semi-insulating GaAs substrate 1.
Periodically repeating InGaAs/GaAs strained superlattice 2
After that, a non-doped InAs active layer 3 is formed. The thickness of the non-doped InAs active layer 3 is approximately 6μ.
m, the electron mobility is approximately 1.9X10'C at room temperature.
I"/V-s, 5.2X10' eta at 77
”/V.S.

[Problem to be solved by the invention] However, since the lattice constant of GaAs is 5.6536 and that of InAs is 6.0584, the degree of lattice mismatch is very large at about 7.1%. Even in the non-doped InAs active layer 3, reduction in electron mobility and deterioration in surface morphology due to the effects of crystal defects cannot be ignored. Further, in order to obtain a certain degree of high electron mobility, it is necessary to form a thick tnAs layer of about several μm.

On the other hand, the problem of lattice mismatch can be avoided by using an InAs substrate, but
When fabricating a FET, due to the leakage current flowing through the substrate
There is a problem with the device that the pinch-off characteristics of the device are not good. The cause of this substrate leakage current is that the energy band gap of InAs is 0.36 eV, and the energy band gap of InAs is 0.36 eV.
It is very small compared to 1.424 eV of [nP] and 1.35eV of
This is thought to be due to the fact that it is very small compared to about 5Ω·1 or more.

In addition, InAs substrates are expensive, and their surfaces deteriorate at relatively low temperatures, making them unsuitable for molecular beam epitaxial growth, which requires heating to remove oxide films and surface cleaning steps. was there.

An object of the present invention is to provide a semiconductor device whose active layer is made of TnAs, which has high electron mobility, and which has good crystal quality, and a method for manufacturing the same.

[Means to solve the problem]

The semiconductor device according to claim (1) includes Ga on an InP substrate.
It has a semiconductor heterostructure in which an InAs active layer is formed through an The GaAs composition ratio changes almost linearly in the thickness direction between the layers, and the GaAs composition ratio is 1.5 x
In the semiconductor device according to claim (1), the semiconductor device according to claim (1) is characterized in that the AlyIrx
The method of manufacturing a semiconductor device according to claim (3), characterized in that a -yAs layer is formed on an InP substrate by buffing Ga, In, □AsAs, and increasing the GaAs composition ratio from 47 to 0 as the thickness increases. It changes linearly, and the GaAs composition ratio composition ratio is 1.5
A step of forming the film by molecular beam epitaxial growth at a growth temperature of 450° C. or less as IO/nm or less;
a. Forming an InAs active layer on the In, -, As buffer layer by molecular beam epitaxial growth at a growth temperature of 400° C. or lower.

[Effect]

According to the configuration of the present invention, when manufacturing a semiconductor heterostructure having an active layer made of InAs, which has high electron mobility and is expected to improve the performance of electronic devices, the degree of lattice mismatch with respect to InAs is lower than that of GaAs. The InP substrate (about 3.2%: lattice constant 5.8) is smaller than the substrate (about 7.1%).
688 people), and further, from a state lattice-matched to InP, the GaAs&ll composition ratio X is gradually decreased in the film thickness direction to finally become InAs.
-y The A3 layer has a GaAs composition ratio change rate of 0.15 or less per buffer layer thickness of 1100 nm, and the GaIn, □AsAs buffing growth temperature by molecular beam epitaxial growth method is 450°C or less + InAs active layer. By forming the growth temperature at 400°C or lower, In
The crystallinity of the As active layer is greatly improved, and the decrease in electron mobility and the deterioration of the surface morphology of the InAs active layer can be suppressed as much as possible.

〔Example〕

Implementation pierced earth A first embodiment of this invention will be described based on FIG.

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the invention. On the semi-insulating InP substrate 4, GaAs composition ratio
The non-doped Gag Tn-x As buffer layer 5 is formed in such a manner that the value decreases approximately linearly with respect to the film thickness. That is, the GaAs composition ratio χ of the non-doped GaXIn, -8As buffer layer 5 is set to 0.47, which is lattice matched to InP at the interface with the semi-insulating InP base Fj, 4, and gradually decreases toward the surface side. . Finally, it is set to 0 (ie, InAs) to form a non-doped InAs active layer 6.

The rate of change in the GaAs composition ratio χ corresponds to the rate of change in the lattice constant, and if this value is large, the density of through-hole defects will increase and will be transmitted into the non-doped [nAs active layer 6.
The crystallinity of the non-doped InAs active layer 6 is reduced.

In this example, the rate of change in the GaAs composition ratio X is 1.5X.
IO-3/nm or less, that is, buffer layer 5 thickness 1100
Good crystallinity is obtained by setting n to 0.15 or less. Under this condition, Gao, a7[n6. , Js.
The film thickness required to change from InAs to InAs is about 8,000.

When growing such a semiconductor heterostructure by molecular beam epitaxial growth, selection of the growth temperature is an important point in order to obtain good crystallinity.

Generally, in crystal growth of a layer containing a high concentration of In, it is known that when the growth temperature is 530°C, the In adhesion coefficient gradually decreases, resulting in a decrease in crystal quality and deviation of the composition from the designed value. Ga0, s+Ina, which is lattice matched to InP,
47AS is grown at temperatures below 500''C.

However, in a layer such as the semiconductor heterostructure of this embodiment, which has a large strain in the buffer layer 5 and whose InAs composition ratio exceeds 53%, it is necessary to grow it at a lower temperature. It is considered that a lower temperature is necessary for the non-doped InAs active layer 6 with a very high In content. In this example, non-doped Ga, In+-
By using a growth temperature of 450° C. for the x As buffer layer 5 and 400° C. for the non-doped InAs active layer 6,
without impairing the excellent electrical properties of As, and
It becomes possible to grow InAs with good surface morphology.

Further, when considering the application of a semiconductor heterostructure to an electric element, an MIS structure is considered because InAs has a large electron affinity and it is difficult to form a Schottky contact.

Then, SiO□ or 5iJ4 is used as the insulating layer of the MIS structure.
However, since there are problems with interface states and distortion, in this example, A
1n1-, As was used. As shown in Figure 1, 2
After forming the non-doped InAs active layer 6 of 000 to 3000 layers, about 500 layers of non-doped A ly I
An n+-y As layer 7 is formed with an A-xAs composition ratio of about 0.5, and is used as an insulating layer.

Implementation (1) As a second embodiment of the present invention, FIG. 2 shows the manufacturing process of an FET using the MIS heterostructure shrimp substrate 20 of the first embodiment.

First, as shown in FIG. 2(a), the MI of the first embodiment
A tungsten gate metal 8, which will become the gate electrode of the FET, is placed on the shrimp substrate 20 of the S heterostructure by a spunter method.
．． Deposit 0 μm.

Next, tungsten gate 9 is formed by photolithography and etching. Furthermore, etching is performed using the tungsten gate 9 as an etching mask,
The non-doped Al yIn, As layer 7 is removed except for the area directly below the tungsten gate 9. The state at this time is shown in FIG. 2(b).

Thereafter, as shown in FIG. 2(C), Si was implanted into 2XIO"Cl11-
2 is implanted and activated by rapid thermal annealing to form an n''-InAs layer 10 to form an ohmic region.

Furthermore, a window was opened in the ohmic electrode part using photolithography, and 100 pieces of Au and 150 pieces of 5N were made.

Evaporate 1000 A u and source by lift-off method.

Drain Ohmink electrode 11. ．． form 12.

Then, in order to separate each FET, separation is performed by mesa etching. Finally, a heat treatment is performed to perform alloying after the ohmic metal trace is deposited to form an FET. The state at this time is shown in FIG. 2(d).

In addition, in the above-mentioned embodiments, the M■S heterostructure was explained as an example, but since the wavelength corresponding to the energy band gap of InAs is in the infrared region, optical devices such as infrared light-receiving devices are manufactured using InAs. In the case of non-doped G according to this invention
It goes without saying that the semiconductor device using the ax In1-z As banff 7 layer 5 and its manufacturing method are effective.

(Effects of the Invention) According to the present invention, the active layer of an electric device or optical device made of InAs can be formed on an InP substrate while maintaining good crystallinity. deterioration can be suppressed as much as possible.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a process for manufacturing a semiconductor device according to a second embodiment of the present invention, and FIG. 3 is a conventional semiconductor device. FIG. 2 is a cross-sectional view of the device. 4... Semi-insulating InP substrate, 5... Non-doped Ga
XIn1-X As banff 7 layers, 6...non-doped I
nAs active layer, 7... non-doped A ly In+
-y As layer 2nd figure H P goro soil milk Tokuyo Hi l Rumor Tetsu Non-dope GaxIn, -x As Ha” Nof 7 layer Non-dope In Shima 1 Non-dope A time 1n1-11 layer

Claims (3)

[Claims] (1) It has a semiconductor heterostructure in which an InAs active layer is formed on an InP substrate via a Ga_xIn_1_-_xAs buffer layer, and the Ga_xIn_1_-_xAs buffer layer has GaA
The s composition ratio x changes almost linearly in the thickness direction from the InP substrate side to the InAs active layer from 0.47, which is lattice matched to InP, and the GaAs composition ratio x
A semiconductor device characterized in that the rate of change of is 1.5×10^-^3/nm or less. (2) Al_yIn_1_-_yA on the InAs active layer
The semiconductor device according to claim 1, wherein an s-layer is formed. (3) A Ga_xIn_1_-_xAs buffer layer is formed on the InP substrate, and the GaAs composition ratio x changes almost linearly with the thickness from 0.47 to 0, and the rate of change of the GaAs composition ratio x is 1.5×10 ^-^3/nm or less by molecular beam epitaxial growth at a growth temperature of 450°C or less; and In on the Ga_xIn_1_-_xAs buffer layer.
A method of manufacturing a semiconductor device, comprising the step of forming an As active layer by the molecular beam epitaxial growth method at a growth temperature of 400° C. or lower.