JPH0439745A - Microprocessor - Google Patents

Abstract

PURPOSE:To grasp the operating state in the course of executing a self-test by storing in advance a second program for interrupting the execution of a first program and outputting the storage contents of a storage means in the case prescribed signal is inputted, in an instruction ROM. CONSTITUTION:In the microprocessor, a built-in instruction ROM 11, and a storage means 2 which stores a value in connection with execution of a test program stored in this instruction ROM 11 and is initialized at the time of resetting the whole are provided, and a signal input terminal 28 for storing a different program for reading out the value stored in the storage means to the outside in the instruction ROM 11 in the course of executing a test program and inputting a signal for executing this program is provided. In such a way, a stored value of the storage means 2 at an arbitrary time point in the course of executing the test program stored in the instruction ROM 11 is read out to the outside, therefore, based on this value, debug is executed easily.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microprocessor with a built-in instruction ROM, and more specifically, it has a self-test function of the arithmetic unit and is initialized by resetting the device. The present invention relates to a microprocessor capable of reading the stored contents of an internal storage means to the outside during execution of a self-test.

[Conventional technology]

As a conventional microprocessor having a self-test function, the inventors of the present invention previously proposed the invention of Japanese Patent Application No. 63332250, which is equipped with a pseudo-random number generator and a signature compression register, and has a pre-built-in 1? We proposed a microprocessor that increases the number of test data by obtaining test data output from a pseudo-random number generator when executing a test program included in OM, thereby reducing the number of steps in the test program. ing.

According to the microprocessor of the invention disclosed in Japanese Patent Application No. 63-332250, the microprocessor can be easily tested using multiple combinations of data without providing test data from the outside.

The invention of the above-mentioned Japanese Patent Application No. 63-332250 will be described below with reference to drawings showing embodiments thereof.

In FIG. 5, reference numeral 1 indicates an address calculation unit (AAU
), and the input side is connected to the P bus 23, although details will be described later.

2 is the bit length 24. Word length 512 (24 bits x 51
It is a built-in 2-port data RAM (2 words), and is equipped with two systems of ports for reading data, and is connected to the above-mentioned address arithmetic unit (AAU) 1 and D bus 24.

3 is the first operation unit input register (RO), 4 is the second
It is an input register (R1) for the calculation unit of the data RAM2.
Each data read port is connected to its respective input side, and is also connected to the D bus 24.

A multiplier (FMPL) 5 inputs and multiplies the outputs of the operation section input registers (RO) 3 and (Ill) 4, the details of which will be described later.

A multiplier output register (MR) 6 holds the multiplication result of the multiplier 5.

7 is an arithmetic unit (FALU) whose details will be described later, but in addition to receiving the outputs of the arithmetic unit input registers (1110) 3, (R1) 4 and multiplier output register (MR) 6, it is also connected to the D bus 24. has been done.

8 is an accumulator (8CC), which mainly holds the calculation result by the calculation unit 7.

9 is an 8-level stack with a program counter (
PC) to value (program counter value) is held as necessary.

A program counter (PC) 10 is an instruction memory for the next instruction to be fetched, specifically a built-in instruction R to be described later.
Sequentially count addresses in OMII.

The built-in instruction ROM II has a capacity of 32 bits x 4 words, and outputs the instruction stored at the address corresponding to the program counter value given from the program counter 10.

Reference numeral 12 denotes a built-in shared memory (CRAM) for instructions and data of 32 bits x 64 words. The values stored in this shared memory 12 can be used both as data words and as instruction words.

Reference numeral 13 denotes an instruction register (IR), which holds the instruction ROMII or the instruction word read from the shared memory 12 and to be executed next.

Reference numeral 14 denotes an instruction decoder, which decodes the instruction word held in the instruction register 13 and controls the operations of each part of this microprocessor based on the decoding result.

Reference numeral 15 denotes a control register for setting the internal operation mode of this microprocessor, and is initialized by reset processing. This control register 15 is connected to the P bus 23 on the input side and to the D bus 24 on the output side.

16 is a direct memory access controller (DMA
), 17 is the serial I10 interface (S11
0).

18 is a data register (OR), and 19 is a signature register.

20 is an interrupt controller, 21 is a clock/reset signal generation circuit (CLK/RST), and 22 is a clock prescaler (CPR).

23 is a P bus that inputs an immediate value into a register according to a command;
4 is each register (reference number 3.4.8.17. '1
8°19) etc. or built-in RAM (reference number 2.
12) is a D bus for transmitting and receiving data between the two, and 25 is an S bus that is controlled by the direct memory access controller 16 during direct memory access to control data transfer between the serial I10 ink face 17 and external memory.

26 is the first interrupt input pin (INTI), 27 is the second
An interrupt input pin (INT2), 28 a test pin (TEST) for setting a test mode, and 29 an IrA pin for setting an II mode which will be described later.

Reference numeral 30 is a 24-bit data input/output terminal, which is used for data transfer between the registers 18, 19, D bus 24, and S bus 25 described above and an external data memory (not shown).

31 is a reset signal (NRESET) input terminal;
It is used to input a reset signal (NRESET) for resetting the entire microprocessor.

Reference numeral 32 denotes a flag register (PR), which indicates the calculation result of the arithmetic unit 7, the level of each input terminal, or the internal operation mode of this microprocessor. This flag register (P
R) 32 is initialized by the reset signal when the above-mentioned reset signal (NRESET) is input.

Next, the operation of the conventional microprocessor shown in FIG. 2 mentioned above will be explained.

This microprocessor uses bits of instruction words.

The bit length of the data word is 32 bits, and the bit length of the data word is 24 bits, and is mainly composed of an address processing section, a coding section, a memory section, and a clock generation section.

First, the address calculation unit 1 has an address mode set in advance by a command (hereinafter referred to as residual control).
According to this set mode, an address for the built-in data RAM 2 or an external data RAM (not shown) is generated.

Address generation by the address calculation unit 1 will be explained below.

As registers related to residual control, the address calculation unit 1 includes an address register that provides an address to the data memory, a base address register that provides a base value for generating an address, and an increment value register that provides an added value of addresses.

It includes a modulo-bit reverse width register that provides the modulo value or focus reverse width, a delta base address register that modifies the base address value during loop instructions, and a delta increment value register that modifies the increment value during loop instructions. , the values of each of these registers are basically set by a mode instruction described below, but they can also be changed by an operation instruction.

The address calculation unit 1 uses ARO as an address register.

It has three registers, R1 and AR2, each controlled by an address calculation circuit. And built-in data R
The address for one readout port 0 of AM2 is designated by register ARO or Al11, and the address is supplied by register AR2 for the other readout port 1.

Regarding register ARO, increment,
Addressing is possible in four modes: modulo, bit reverse, and repeat, and base address value,
It is possible to set the increment value, modulo value and bit reverse width independently.

Furthermore, the registers ARI and AR2 can be addressed in two modes, increment modulo, and the base address value, increment value, and modulo width can be set independently, similar to the register API.

Furthermore, direct addressing is also possible for port 1.

Next, the configuration of the calculation section will be explained.

The arithmetic unit is designated by reference numeral 3.4.5.6゜7 in Fig. 5.
The arithmetic unit input registers RO and R1, indicated by 8 and 8, are composed of a multiplier output register, arithmetic unit, and an accumulator.

The format of the calculation data is 16 bits for the mantissa.

24-pin floating point data with 8-bit exponent and 24
Thirty-one types of operations are performed on three types of data: bit fixed-point data and 24-bit logic data.

The multiplier 5 includes an operation section input register (IiO) 3. (R1
) 4, the floating point multiplication result is output to the multiplier output register 6 every cycle regardless of the instruction. However, if the ALU field of the operation instruction specifies an operation on fixed-point data, the upper or lower 16 of the operation unit input register (RO) 3 and operation unit input register (R1) 4 The upper or lower 24 bits of the bit multiplication result (32 bits) are output to the multiplier output register 6.

In the arithmetic unit 7, an arithmetic unit input register (RO) 3 or an accumulator 8 is connected to the X input as an input register.
An arithmetic unit input register (Ill) 4 or a multiplier output register 6 is provided for the y input, and the arithmetic operation is executed in one machine cycle according to the contents of the operation instruction, and the arithmetic result is output to the accumulator 8.

Next, an overview of the memory section will be described.

In FIG. 5, the memory sections are designated by reference numbers 2, 11 and 12
2-bit data RAM and instruction ROM shown in .

Shared RA? It is composed of I. Also, there is an instruction R inside.
An instruction memory space of 4 words is allocated as OMII.

As a data memory space, a 512-word 2-point RAM 2 is allocated inside the microprocessor, and a 60-word area is allocated outside the microprocessor as an extended data memory space. Further, four words are allocated as a shared memory space 12 between the instruction memory and the data memory.

Next, the clock generation section will be explained.

The black and white generators are designated by reference numerals 21 and 2 in FIG.
It is composed of a clock/reset signal generation circuit and a clock prescaler shown at 2.

This clock generation section divides the frequency of an external clock using a clock prescaler 22 according to a clock prescaler value set by an instruction, thereby generating a non-overlapping four-phase clock.

The clock/reset signal generation circuit 21 generates a reset signal N.
When RESET becomes active, the program counter 10 is normally reset to a predetermined fixed address.
When the reset signal NRESET becomes inactive, the first input input bin (INTI) 26. If the second interrupt input pin (INT2) 27 is active, the contents of the data register 18 are transferred to the program counter 10. By using this function, by writing arbitrary data into the data register 18 from the outside in advance, it is possible to perform a reset process to start a program from an arbitrary address.

Next, the instruction formant in the microprocessor configured as described above will be described.

The instruction word length is 32 bits, and the instructions are broadly classified into four types: sequence instruction group, mode instruction group, operation instruction group, and load instruction group.

In the sequence instruction group, there are 8 instructions mainly related to branching.
In the type and mode instruction group, there are seven types of instructions that set data to each register, in the operation instruction group, there are seven types of instructions related to calculations, and in the load instruction group, there are two types of instructions that set FIp values to registers. Except for the load instruction group, each instruction in the group is determined based on the decoding result of the upper 5 bits (27th to 31st bits), and the remaining 27 bits are allocated to each field shown below.

First, in the sequence instruction group, fields are allocated as shown in fa+ in FIG.

FIG. 6(a-1) shows the bit arrangement of the sequence instruction.

The 23rd bit to the 26th bit are as shown in Fig. 6 (a-5, 6,
As shown in 78), this is a field for specifying a change in the initial value of a loop counter or a change in addressing modification during a loop. The 19th bit and the 23rd bit are fields for setting branch conditions for conditional jumps, as shown in FIG. 6(a-4). The 4th to 6th bits are fields that specify the destination address.
The 4th to 6th bits are shown in Figure 6 (a-3).
As shown in , this is also a field that specifies a register for an indirect jump whose destination address is the contents held in the register.

In the mode command group, fields are allocated as shown in FIG. 6 (bl).

FIG. 6(b-1) shows the bit arrangement of the mode command.

The 26th bint is Residual!, as shown in Figure 6 (b-3). Internal 2 boat RAM2 boat 0 by 11m
Use register ARO as the address of register A
This field indicates whether RI is used. The 25th bit is a field indicating whether register ARO or register ARI is used as the address of the lower 9 bits of the external data RAM, as shown in FIG. 6(b-4).

The 4th bit to the 22nd bit are fields in which values for mode setting are written, as shown in FIG. 6(b-5). The 0th to 3rd bits are fields for specifying to which register a value is to be set.

In the operation instruction group, fields are allocated as shown in FIG. 6 tc+.

FIG. 6(c-1) shows the bit arrangement of the operating instruction.

The 26th bit is a field indicating whether direct addressing is to be performed. The 23rd bit to the 25th bit are fields each indicating whether or not registers ARO, ARI, and AR2 are updated by residual control. The 22nd pinpoint converts the contents of the data register into external data R.
The 21st bit indicates whether to write to AM or not.
This field controls whether or not to read data from M to the data register. The 1920th bit transfers the contents of the built-in RAM 2 written at the address indicated by the address register to the arithmetic section input register (RO) 3. (R1) This field controls whether to write to 4 or not. The 17th and 18th bits are a field for selecting the input register to the arithmetic unit 7. 12th bit to 16th and 7) are shown in Fig. 6 (c-
As shown in 8), this field specifies the operation of the arithmetic unit 7, and is particularly called the ALU field. Chapter 10.11
The bit is a field for specifying an accumulator into which the calculation result of the calculation unit 7 is input, as shown in FIG. 6(c-4).

The 8.9th bit is a field for specifying the output achievator, as shown in FIG. 6(c-5). The fourth bit to the seventh pin are fields indicating the source register for data transfer performed via the D bus 24, as shown in FIG. 6 (c-6). The 9th to 3rd bits are fields for specifying the destination register for data transfer via the D bus 24, as shown in FIG. 6(c-7).

The ALII field shown in FIG. 6(c-8) will be explained in more detail. Note that the two human inputs to the computing unit 7 are assumed to be X input and X input, respectively, and the outputs are assumed to be two outputs.

NOP is an instruction that causes the arithmetic unit 7 to perform no calculation, and neither the X input nor the X input is input to the arithmetic unit 7, and therefore, no two outputs are performed.

INV is an instruction that regards the X input data as floating point data, inverts the sign, and outputs two.

ABS is an instruction that treats the X input data as floating point data and outputs two of its absolute values.

SGN is an instruction that treats the X input data and the X input data as floating point data, multiplies the absolute value of X by the sign of y (1 for a positive number, -1 for a negative number), and outputs the result in Z. It is.

800 is an instruction that treats the X input data and the X input data as floating point data, adds them, and outputs two.

SUB is an instruction that treats the X input data and the X input data as floating point data, subtracts them, and outputs two.

MAX is an instruction that treats and compares the data of the X input and the data of the X input as floating point data, and outputs the larger one as two outputs.

MIN is an instruction that treats the X input data and the X input data as floating point data, compares them, and outputs the smaller one as two outputs.

T) IR is an instruction that outputs two data from the X input as is.

XFT is an instruction that treats X input data as fixed-point data, converts it into floating-point data according to the mode set in the control register 15, and outputs two.

PXT is an instruction that treats the X input data as floating point data, converts it into fixed point data according to the mode set in the control register 15, and outputs two.

SRI is an instruction that regards the data at the X input as logical data, shifts it to the right by 1 bit, and outputs 2.

SLI is an instruction that regards the data at the X input as logical data, shifts it to the left by 1 bit, and outputs 2.

SL2 is an instruction that regards the data at the X input as logical data, shifts it to the left by 2 bits, and outputs 2.

SL4 is an instruction that regards the data of the X input as logical data, shifts it by 4 points to the left, and outputs 2.

SL8 is an instruction that regards the data at the X input as logical data, shifts it to the left by 8 bits, and outputs 2.

These<7) SRI, SLI, SL2. SL4.
SL8? The data shifted in is all 0.

AND is an instruction that regards the data of the X input and the data of the X input as logical data, performs a logical product, and outputs two.

OR is an instruction that treats the data of X input and the data of y people as logical data, performs a logical sum, and outputs two.

EOR is an instruction that regards the data of the X input and the data of the X input as logical data, performs an exclusive OR, and outputs two.

NOT is an instruction that regards the data of the X input as logical data, performs a logical negation, and outputs two outputs.

MAD is the lower 1 of the X input data and the X input data.
This instruction performs fixed-point addition on 6 bits and outputs 2 outputs, but the exponent part of the input data is ignored and the upper 8 of the 2 outputs are
“0” is output to the bit.

The ESB is the top 8 of the X input data and the X input data.
This instruction performs fixed-point subtraction on bits and outputs 2 bits, but the mantissa part of the input data is ignored, and the lower 16 bits of the 2 outputs are output as 8000K'' (w represents a hexadecimal number).

IMUL does nothing to the arithmetic unit 7, and the multiplier 5
This is an instruction to perform fixed-point multiplication on .

IADD is an instruction that treats X input data and X input data as fixed point data, adds them, and outputs two.

l5UB is an instruction to subtract the X input data from the X input data and output two by regarding the X input data and the X input data as fixed point data.

IADC is an instruction that treats the X input data and the X input data as fixed point data, adds these two numbers to the carry bit in the flag register (PR) 32, and outputs two.

l5BB regards the X input data and the X input data as fixed point data, subtracts the X input data from the X input data, further subtracts the carry pinto in the flag register (PR) 32, and outputs 2. It is a command.

ASRI is an instruction that treats the X input data as fixed point data, shifts it to the right by 1 bit, and outputs 2.

ASR2 is an instruction that treats the X input data as fixed point data, shifts it to the right by 2 bits, and outputs 2.

ASR4 is an instruction that treats the X input data as fixed-point data, shifts it to the right by 4 bits, and outputs 2.

ASR8 is an instruction for outputting 8 points □ right shift by regarding the data of the X input as fixed point data.

These (7) ASlil, ASR2, ASR4, AS
The shift-in data in R8 is the sign bit (the most significant focus of the X input).

The load instruction group is divided into load instructions and long load instructions by the most significant three bits.

In the load instruction, fields are allocated as shown in FIG. 6 (dl).

FIG. 6(d-1) shows the bit arrangement of the load instruction.

The 28th bit 7 is a field for controlling writing to the external data RAM, as shown in FIG. 6(d-2). The 26th and 27th bits are as shown in FIG. 6(d-3) (if the register to which the immediate value is written is accumulator (ACC) 8, then the unillustrated ^CCO ~ This is a field that specifies which accumulator in ACC3 it is.The 23rd to 25th bits are fields that control updating of the contents of the address register by residual control, as shown in Figure 6 (d-3). The 22nd focus is shown in Figure 6 (d
-5), the MS of the 24 bits of the D bus 24
This field controls whether the 18 vias on the B side are written to the register or the 18 pins on the LSB side are written to the register. The 4th bit to the 21st pin are fields for specifying the immediate value to be written into the register. 0th bit to 3rd bit
The bit is a field that specifies the register into which an immediate value is written, as shown in FIG. 6 (d-6).

The long load instruction has fields allocated as shown in FIG. 6(e).

FIG. 6(e-1) shows the bit arrangement of the long load instruction.

The 28th pin transfers the contents of the data register to external data RA.
This is a field that controls whether or not to write to M.
The bit to 27th bit is a field for specifying an immediate value. The 0th to 3rd bits are registers into which immediate values are written, as shown in FIG. 6(e-2).Next, the operating modes of the conventional microprocessor as described above will be explained.

In addition to the normal mode, the microprocessor has the following test modes as operating modes.

First, the IIA (Internal T
structure ROM/RAM Access
)mode.

A pin test mode in which the output state or output level of the data input/output terminal 305 (not shown) and other input/output terminals can be set independently of the internal operation of the microprocessor.

Since it is difficult to observe in the normal mode, the values of the bus 24 and the program counter 10 are output to the outside from the data input/output terminal 30 and other input/output terminals not shown.
EEP mode.

Data register 18 or serial I1 by executing the instruction.
When a serial input register (not shown) in the 0 interface 17 is used as a source register for bus transfer using the D bus 24, a pseudorandom number generator (not shown) in the signature register 19 is used instead as a source register for bus transfer using the D bus 24. When the data register 18 or the serial output register (not shown) in the serial I10 ink face 17 is used as a destination register for bus transfer using the D bus 24, the data register 19 in the fern nature register 19 can be used instead. A self-test mode in which a data compressor (not shown) is used as a destination register for bus transfer.

Note that a pseudo-random number generator and a data compressor (not shown) in the signature register 19 are independent from each other, and are initialized by reset processing.

Further, the pseudorandom number generator outputs a new random number each time it is accessed as a source register, and the data compressor performs signature compression of data output from the source register each time it is accessed as a destination register.

Furthermore, the above-mentioned mode switching is performed by a combination of the logic levels of the input signals to the τEST mode setting signal input terminal 28 and the IIA mode setting terminal 29.

Next, a method of testing the arithmetic unit 7 using the self-test mode among the above-mentioned test modes will be described.

The test of the calculator 7 is performed by executing each calculation with various input values and examining the results. In addition, for certain types of calculations (for example, ADC calculations, etc.), the value of the flag register (PR) 32 set by the previously executed calculation is used, so the history of calculation execution becomes a problem. Become.

For this reason, a case will be considered in which a random number output from a pseudo-random number generator is used as the input value of the arithmetic unit 7, and the result of the calculation is compressed by a data compressor.

Each time a command specifies, for example, the data register 18 as a source register for bus transfer using the D bus 24, new pseudo-random number data is obtained.

This pseudo-random number data is input to the arithmetic unit input register of the arithmetic unit 7 (
110)3. By transferring the data to (R1)4, various calculation manual values can be obtained.

Furthermore, by bus-transferring the calculation results using the D bus 24 and specifying, for example, the data register 18 as the destination register, the calculation results can be compressed.

The operations described above can be realized with a few instructions, and by using multiple loops, it is possible to test an arithmetic unit using a large number of pseudo-random numbers with a small number of instructions. It is possible to determine whether the test execution result is normal or not by comparing the final result after the test with the final signature output by a microprocessor that has been confirmed to operate normally.

Next, FIG. 7 shows an example of a self-test program for the arithmetic unit 7 of a microprocessor having such a test circuit, and FIG. 8 shows a flowchart showing its processing procedure.

As shown in FIG. 8 (al), this self-test program is structured so that a large number of tests can be performed with a smaller number of instructions by using a double loop.

8th issue) is a flowchart showing the processing procedure of module 1.

First of all, from the pseudo-random number generator in the middle register 19 to the arithmetic unit input register (RO) 3. (R1) 4, performs an operation, transfers the result of the operation to the data compressor in the signature register 19, and performs compression. At the same time, for each - operation, the flag register (PR) 32
Check the contents of flag register (FR) 3.
The conditional jump test according to the contents of 2 is also shown in Figure 8 (d).
This is done in module 3 shown below.

This routine attempts to reduce the number of test program steps by combining -manual and two-manpower calculations.

FIG. 8 (C1 is a flowchart showing the processing procedure of module 2.

This module 2 is a modification of module 1, and is a routine that receives the carry of the previous instruction stored in the flag register (PR) 32, performs an operation, and transfers the data to the data compressor in the signature register 19. be.

In FIG. 8, three types of operations are used to represent operation instructions, but for all operations that can be executed by the operation unit 7 in FIG.
IJ field operations NOP, [NV, ABSS
GN ADD SOB, MAX, MIN, T
HR, XFT, FXT, 5RISLI SL2
．． SL4. SL8 AND, OR, E
OR, NOT, MADESB IMUL, IA
DD, l5UB, IADC, l5BB, ASRl
, ASR2ASR4, ASR8.

The program shown in FIG. 7 is a combination of these modules expressed as one program. This program consists of a small number of words, approximately 120 words.

FIG. 9 shows that the self-test program shown in FIG.
FIG. 2 is a schematic diagram showing how the built-in instruction ROMII shown in the figure is configured on the memory space.

By adopting such a memory space configuration, in the normal mode, a user program whose start address is the address "oooo" is executed. However, when executing a self-test, the above-described self-test is executed by using the reset function as the self-test mode and using the above-mentioned recent start processing that allows a recent start from any address.

[Problem to be solved by the invention]

In conventional microprocessors such as those mentioned above, test results are determined only based on the final result of signature compression through self-testing, so it is only possible to determine whether or not the arithmetic unit of the microprocessor that executed the test is normal. Therefore, there is a problem in that it is not possible to specify which part of the arithmetic unit of the microprocessor is defective.

The present invention was made in view of these circumstances, and
By interrupting self-test execution at any timing, executing the debug program, and reading the contents of registers or flags initialized by the reset function to the outside of the microprocessor, the mid-test results can be identified and the microprocessor The purpose of the present invention is to provide a microprocessor that is capable of grasping the operating state of the processor during self-test execution.

[Means to solve the problem]

The microprocessor of the present invention has built-in instructions 1
10M and this command 1? A storage means that stores values as the test program stored in the OM is executed and is initialized when the entire system is reset, and reads out the values stored in the storage means while the test program is being executed. A separate program for this purpose is stored in the instruction ROM, and a signal input terminal is provided for inputting a signal for executing this program.

[Effect]

In the microprocessor of the present invention, the stored value of the storage means at any time during execution of the test program stored in the instruction ROM is read out to the outside, so debugging can be easily performed based on this value.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the drawings showing embodiments thereof.

In FIG. 1, reference numeral 1 is an address calculation unit (AAU
), and the input side is connected to the P bus 23, although details will be described later.

2 is the focus length 24. Word length 512 (24 bits x 51
2 words), the R2 port data RA- is provided with two systems of ports for reading data, and is connected to the address arithmetic unit (AAU) 1 and the D bus 24 described above.

3 is the first summer part input register (RO), 4 is the second
It is an input register (R1) for the calculation unit of the data RAM2.
Each data read port is connected to its respective input side, and is also connected to the D bus 24.

Reference numeral 5 denotes a multiplier (IMPI), which will be described in detail later, but which inputs and multiplies the outputs of operation section input registers (RO) 3 and (R1) 4.

A multiplier output register (MR) 6 holds the multiplication result of the multiplier 5.

7 is an arithmetic unit (FALU) whose details will be described later, but in addition to inputting the outputs of the arithmetic unit input registers (RO) 3, (R1) 4 and multiplier output register CMR) 6,
It is also connected to the D bus 24.

8 is an accumulator (ACC), which mainly holds the result of calculation by the arithmetic unit 7;

9 is an 8-level stack with a program counter (
PC) 10 (program counter value) is held as necessary.

Program counter (PC) IQ is the instruction memory of the next instruction to be executed, specifically the built-in instruction R described later.
Sequentially count addresses in OMII.

The built-in instruction ROM II has a capacity of 32 pins x 4 words and outputs the instruction stored at the address corresponding to the program counter value given from the program counter 10.

Reference numeral 12 denotes a built-in shared memory (CRAM) for instructions and data of 32 pins x 64 words. The values stored in this shared memory 12 can be used both as data words and instruction words.

Reference numeral 13 denotes an instruction register (IR), which holds the instruction ROMII or the instruction word read from the shared memory 12 and to be executed next.

Reference numeral 14 denotes an instruction decoder, which decodes the instruction word held in the instruction register 13 and controls the operations of each part of this microprocessor based on the decoding result.

Reference numeral 15 is a control register for setting the internal operating mode of this microprocessor.

Initialized by default processing. This control register 15 is connected to the P bus 23 on the input side and to the D bus 24 on the output side.

I6 is a direct memory access controller (DMA)
), 17 is serial I10 ink 7z i, 2. (
Stro) 18 is a data register (DR), and 19 is a signature register.

20 is an interrupt controller, 21 is a clock/reset signal generation circuit (CLK/R5T), and 22 is a cross scaler (CPR).

23 is a P bus that inputs an immediate value into a register according to a command;
4 is each register (reference number 3.4.8.17.18゜1
9) etc. or built-in RAM (reference number 2.12
), and 25 is an S bus that is controlled by the direct memory access controller 16 during direct memory access to control data transfer between the serial I10 interface 17 and external memory.

26 is the first interrupt input bin (INTI), 27 is the second
An interrupt input pin (INT2), 28 a test pin (TEST) for setting a test mode, and 29 an IIA pin for setting an IIA mode, which will be described later.

30 is a 24-pin data input/output terminal, which is used for data transfer between the registers 18, 19, D bus 24, and S bus 25 and an external data memory (not shown).

31 is a reset signal (NRESET) input terminal;
It is used to input a reset signal (NRESET) for resetting the entire microprocessor.

32 is a flag register (PR), which indicates the calculation result of the arithmetic unit 7, the level of each input terminal, or the internal operation mode of this microprocessor.
R) 32 is initialized by the reset process when the above-mentioned reset signal (NRESET) is input.

The above configuration is basically the same as the invention of Japanese Patent Application No. 63-332250 filed by the inventors of the present invention, which was previously described as a conventional example.

Reference numeral 33 is a clock signal (CLK) input terminal, and the microprocessor of the present invention operates in synchronization with the clock signal CLK input from this clock signal input terminal 33.

Reference numeral 34 is a non-maskable interrupt signal (NMI) input terminal, and the non-maskable interrupt signal NMI is an input signal to this non-maskable interrupt signal input terminal 34 when the microprocessor of the present invention is in a state other than during reset processing.
When becomes active, a subroutine is called at a specific address in the instruction space.

In the microprocessor of the present invention, the structure, operation, instruction form, self-test program of the arithmetic unit 7, etc. of each of the above-mentioned components having the same reference numerals as in the conventional example are the same as in the conventional example. Since they are exactly the same, their explanation will be omitted.

FIG. 2 shows the processing necessary to interrupt the self-test during execution of the microprocessor shown in FIG. 1 and read out the contents of the flag register (FR) 32 at the time of interruption to the outside of the microprocessor. It is a flowchart showing a procedure.

First, in step Sl, the self-test program is reset-started using a reset process for starting program execution from an arbitrary address.

Next, in step S2, the operating mode of the microprocessor is set to self-test mode, and execution of a self-test using signature register 19 is started.

In step S3, execution of the self-test is continued until a condition for interrupting the self-test is met.

In step S4, in order to interrupt the self-test, the non-maskable interrupt signal NMI input to the non-maskable interrupt signal input terminal 34 is set active and the debug program is started.

In step S5, the operating mode of the microprocessor is set to PEEP mode so that the data transferred using the D bus 24 is outputted from the data input/output terminal 30 as is.

In step S6, the debug program executes an instruction to set the flag register (PR) 32 as a source register for bus transfer using the D bus 24, and reads the value of the flag register (PR) 32 to the outside of the microprocessor. put out.

An example of a debug program for performing such operations is shown in FIG. 3, and a flowchart showing the processing procedure is shown in FIG. 4.

At step 311 in FIG. 4, a jump instruction to the debug program located at the subroutine call address at the time of execution of the non-maskable interrupt is executed. Then, in step S12, an instruction using the data register 18 as a source register for bus transfer using the D bus 24 is executed.

In FIG. 3, the label "NMIADD:" indicates the subroutine call address when a non-maskable interrupt is executed.
Further, the label "DEBAG:" indicates the start address of the debug program.

It goes without saying that in the above-described debug program, an instruction for outputting the contents of other storage means of the microprocessor to the outside of the microprocessor may be added in addition to the flag register (PR) 32.

Further, the above-mentioned debug program is configured with an instruction to transfer the contents of the storage means initialized in the reset processing of the microprocessor to the storage means inside the microprocessor that is not initialized, and the contents of the storage means that are not initialized are A program for reading out the microprocessor to the outside of the microprocessor may be further provided in the built-in instruction ROM, and the program may be executed using a reset process that starts execution from an arbitrary address.

Furthermore, in order to determine the timing of interrupting the self-test program, it is also possible to use the intermediate result of signature compression output from the data input/output terminal 30 during execution of the self-test.

Furthermore, a configuration is also possible in which a control signal other than the non-maskable interrupt signal NMI that is not used in the self-test program is used to interrupt the self-test.

〔Effect of the invention〕

As described in detail above, according to the present invention, data held in the internal storage means necessary for investigating the cause of an abnormality in the self-test result of a microprocessor using a small number of debugging programs of about a few words can be stored. Since the information can be easily read out from the microprocessor, the cause of a defect can be quickly and easily identified during the development stage of the microprocessor, and the time required to develop the microprocessor can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a microprocessor according to the present invention, FIG. 2 is a flowchart showing a procedure for operating a debug program during a self-test of the arithmetic unit, and FIG. 3 is a block diagram showing the configuration of a microprocessor according to the present invention. A schematic diagram showing an example of a list of debug programs stored in the built-in instruction ROM of the microprocessor, FIG. 4 is a flowchart showing its operating procedure, and FIG. 5 shows an example of the configuration of a conventional microprocessor having a self-test function. The block diagram and FIG. 6 are schematic diagrams showing instruction formants commonly provided in the microprocessor of the present invention whose configuration is shown in FIG. 1 and the conventional microprocessor whose configuration is shown in FIG. , FIG. 7 shows the built-in instruction RO gate stored in the built-in instruction RO gate which is commonly provided in the microprocessor of the present invention whose structure is shown in FIG. 1 and the conventional microprocessor whose structure is shown in FIG. FIG. 8 is a schematic diagram showing an example of a self-test program list, FIG. 8 is a flowchart showing its operating procedure, FIG. 9 is a microprocessor of the present invention whose structure is shown in FIG. 1, and FIG. 5 whose structure is shown. 1 is a schematic diagram showing an instruction memory space of a built-in instruction ROM commonly provided in conventional microprocessors; FIG. 2...Built-in data RA? I 7...Arithmetic unit 1
1...Built-in instruction ROM 19...Signature register 20...Interrupt controller 26...
1st interrupt input pin 27... 2nd interrupt manual pin
28...TEST mode setting signal input terminal 30.
. . . Data input/output terminal 31 . . . Reset signal input terminal 32 . . . Flag register 34 .

Claims (1)

[Claims] (1) an arithmetic unit, a pseudo-random number generator and a data compressor for testing the arithmetic unit, an instruction ROM storing a plurality of instructions constituting a program, and the pseudo-random number generator and data compressor. a first input terminal for inputting a signal for setting a mode that can be used, and when the mode is set, the output of the data compressor or the output of the data compressor and the output of the data compressor; and a first output terminal for outputting a comparison result with an expected value to the outside, and in the mode, inputs specific data or a pseudorandom number output from the pseudorandom number generator to the arithmetic unit, and outputs the calculation result. The first program that executes a series of processes for inputting
In the microprocessor stored in M, a storage means is initialized by a reset process and stores values as the first program is executed, and a second output is used to output the stored contents of the storage means to the outside. a terminal, and a second input terminal, and when a predetermined signal is input from the second input terminal during execution of the first program, the execution of the first program is interrupted and the contents stored in the storage means are saved. A microprocessor characterized in that a second program to be output to the outside via the second output terminal is stored in the instruction ROM.