JPH0439785B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device in which circuit connection is performed using a master slice method, and is effective for preventing electrostatic damage in semiconductor integrated circuit devices constituting a gate array, for example. It is related to technology.

[Background technology]

With the advancement of semiconductor integrated circuit manufacturing technology,
Elements are becoming increasingly finer. With the miniaturization of such elements, there is an increasing demand for high reliability in preventing electrostatic discharge damage.

The inventor of the present application has developed a semiconductor device that has various circuit functions by forming a basic pattern in which elements constituting a circuit are appropriately arranged, and by changing only the wiring mask that interconnects the elements as necessary. We thought of using the master slicing method to obtain integrated circuit devices to strengthen the electrostatic damage prevention function.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device in which the electrostatic damage prevention function is improved without increasing the number of substantial elements.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows. In other words, by connecting an element that is not used in the input circuit to an external terminal used as an input terminal using the master slice method and using it as a capacitor for preventing electrostatic damage, the electrostatic damage prevention function is strengthened. It is something to do.

〔Example〕

The drawings show a circuit diagram of essential parts of an embodiment of the present invention. Each circuit element in the figure is formed on a semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique.

In the embodiment shown in the figure, the input and output of a gate array constituted by CMOS (complementary MOS) consisting of a p-channel MOSFET (insulated gate field effect transistor) and an n-channel MOSFET, although not particularly limited. Part of the circuit is shown.

In other words, the resistor R and MOSFET Q1 constitute a known electrostatic damage prevention circuit, and the p-channel
MOSFETQ2 and n-channel MOSFETQ3 are formed as elements constituting an input circuit. Furthermore, the p-channel MOSFET Q4 and the n-channel MOSFET Q5 are formed as elements constituting an output circuit.

When pad P1, which is connected to an external terminal by bonding or the like, is used as an input terminal, in this embodiment, the basic patterns constituting the input circuit and output circuit are connected as shown in the figure by the master slice method. Ru. That is, the pad P1 is connected to the input terminal T1 of the electrostatic damage prevention circuit. Its output side terminal T2 is
Connected to the gates of MOSFETQ2 and Q3. In addition, the drains of these MOSFETQ2 and Q3 are
They are commonly connected and connected to wiring that leads to an internal circuit at the next stage (not shown). The source of MOSFETQ2 above is connected to the power supply voltage line Vcc, and
The source of MOSFETQ3 is connected to the ground potential line of the circuit. In this way, the input circuit is configured.

In this example, we configure the output circuit
Focusing on the fact that MOSFETs Q4 and Q5 are not used, these MOSFETs Q4 and Q5 are effectively utilized as capacitive elements for preventing electrostatic damage.

That is, although not particularly limited, the above
By making the drains of MOSFETQ4 and Q5 common,
Connect to the above pad P1. Also, these
In order for MOSFETQ4 and Q5 to function as mere capacitive elements, their gates and sources are shared and connected to the power supply voltage line Vcc and ground potential line, respectively, so that they are constantly turned off. .

In addition, the same resistance R' and MOSFET Q1' as above,
With the basic pattern consisting of Q4' or Q5',
When pad P2 is used as an output terminal, as shown in the figure, MOSFETQ
The drains of Q4' and Q5' are shared and connected to the pad P2. Also, these MOSFETQ
The gates of 4' and Q5' are connected to a common signal line formed by an internal circuit (not shown) and to which a signal to be output is transmitted, and the sources of each are connected to the power supply voltage line Vcc and the circuit ground line. be done.

In such an output circuit, the drain regions of MOSFETs Q4' and Q5', which are relatively large in size, have sufficient withstand voltage against static electricity from external terminals, so the above-mentioned electrostatic damage prevention circuit, etc. No need to connect.

〔effect〕

(1) When a capacitor that utilizes the drain region of a relatively large output MOSFET is connected to the input terminal P1, the capacitance value of the capacitor that receives the charged charge increases, so the voltage (V
=Q/C) and by integrating the parasitic capacitance and the equivalent resistance, the ability to prevent electrostatic damage can be greatly improved.

(2) Since it utilizes unused elements without using any special circuit elements, it is possible to obtain the effect that the actual degree of integration is not reduced.

(3) In particular, in semiconductor integrated circuit devices composed of gate arrays, an input element and an output element are formed on one external terminal, so an electrostatic damage prevention circuit is required. In this input circuit, it is possible to effectively utilize unused output elements.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, in the above example,
The drains of MOSFETs Q4 and Q5 may be connected to the output terminal T2 of the electrostatic breakdown prevention circuit. Alternatively, only one of the output MOSFETs Q4 and Q5 may be used.

Further, the specific circuit configuration of the input circuit and the output circuit may be a circuit having a gate function, a tri-state (three-state) output function, or the like in addition to the above-mentioned inverter circuit.

[Field of Application] The above explanation mainly focuses on the field of application that is the background of the invention made by the inventor of the present application.
Although we have explained the case where it is applied to a CMOS gate array, it is not limited to this, and for example, an ECL (emitter
It can be widely used in various semiconductor integrated circuit devices whose circuit functions are designed using the master slice method, such as gate arrays constructed using coupled logic (coupled logic) and the like.

[Brief explanation of drawings]

The drawing is a circuit diagram showing an embodiment of the main part of the present invention.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device whose circuit function is set by the master slice method, an element not used in the input circuit function is connected to an external terminal used as an input terminal as a capacitor for preventing electrostatic damage. A semiconductor integrated circuit device characterized by: 2. A patent claim characterized in that each signal external terminal is formed with an element constituting an input circuit and an element constituting an output circuit, and the unused elements are output elements. The semiconductor integrated circuit device according to item 1. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the semiconductor integrated circuit device constitutes a gate array.