JPH043980A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve frequency characteristic of a transistor and to further improve integration by connecting the gate electrode of an insulated gate type field effect transistor to a first outer terminal via a first metal wiring having small specific resistance value and connecting a source region to a second outer terminal via a second metal wiring formed on a conductive layer having smaller specific resistance value than that of the gate electrode and different from the first wiring. CONSTITUTION:A metal wiring 8G is formed on an upper conductive layer than a gate electrode 6 of an insulated gate field type field effect transistors Q, a metal wiring 10S is formed on an upper conductive layer than the wiring 8G, and the wiring 8G is formed of thinner film thickness than that of the wiring 10S. With the structure, the processing accuracy of the wiring 8G is enhanced and since the processing accuracy of the electrode 6 of the transistor Q is enhanced correspondingly, the occupying area of the transistor Q is reduced, and the integration of a semiconductor device of a single structure can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to a single-piece structure semiconductor device equipped with a transistor.

[Conventional technology]

A so-called power transistor is known as a single-structure semiconductor device equipped with a vertical insulated gate field effect transistor. In this insulated gate field effect transistor, a drain region (n-type semiconductor region) is formed from a semiconductor substrate. A channel forming region (p-type semiconductor region) is formed on the main surface of the train region. The source region (n-type semiconductor region) is formed on the main surface of the channel formation region. The gate electrode is formed between the train region and the source region with a gate insulating film interposed on the channel formation region. The gate electrode is usually formed of a gate material such as a polycrystalline silicon film.

Insulated gate field effect transistors are known, for example, from Japanese Patent Application Laid-open No. 6
As described in Japanese Patent No. 1-248475, each of the gate electrode and the source region is independently connected to an external terminal (ponding pad). This type of single structure semiconductor device is different from an FFWIc or an LSI in which a plurality of transistors are integrated as a circuit system, and has a single layer structure of aluminum wiring. That is, the wiring connecting the gate electrode and the external terminal, the wiring connecting the source region and the external terminal, and the external terminal are composed of single-layer aluminum wiring. The above-mentioned ICs and LSIs are constructed with a multilayer structure having two or more wiring layers in order to reduce the area occupied by the wiring due to the routing of the wiring. On the other hand, in a semiconductor device with a single structure, there is a gap between the gate electrode and the external terminal.
By simply connecting the source region and the external terminals with wiring, there is no need for cross wiring or a multilayer structure.

Furthermore, since a single structure semiconductor device requires an additional manufacturing process, it is constructed with a single layer structure of aluminum wiring.

The gate electrode of the insulated gate field effect transistor is formed on most of the main surface of the semiconductor substrate.

The aluminum wiring connecting the gate electrode and the external terminal is formed as a connecting wiring in a planar long and narrow pattern, and occupies a small portion of the main surface of the semiconductor substrate. On the other hand, the aluminum wiring connecting the source region and the external terminal occupies most of the area on the main surface of the semiconductor substrate, excluding the above-mentioned part of the area.

[Problem to be solved by the invention]

The present inventor discovered the following problems prior to developing a single-structure semiconductor device equipped with an insulated gate field effect transistor.

(1) The wiring width of the aluminum wiring connecting between the gate electrode of the insulated gate field effect transistor and the external terminal is small, and the resistance value of this aluminum wiring increases. Therefore, the switching speed of the insulated gate field effect transistor decreases, and the frequency characteristics of the semiconductor device deteriorate.

(2) An element isolation insulating film is formed on the main surface of the semiconductor substrate below the aluminum wiring connecting the gate electrode and the external terminal. This element isolation insulating film is formed in a non-active region of a semiconductor substrate, and an insulated gate field effect transistor cannot be mounted on this non-active region. For this reason, the area occupied by the active region of the semiconductor substrate in the insulated gate field effect transistor is reduced, the gate width cannot be secured sufficiently, and the amount of current flowing between the source region and the drain region is reduced, resulting in a reduction in drive capacity. decreases. Additionally, in order to increase the drive capability of an insulated gate field effect transistor, it is necessary to increase the area of the active region of the semiconductor substrate.
The degree of integration of semiconductor devices decreases.

(3) In order to solve the problem (1), if the number or area of aluminum wiring is increased, the area occupied by the aluminum wiring connecting the source region and the external terminal is conversely reduced. This limits the amount of current that can be supplied to the source region of an insulated gate field effect transistor.
Driving ability decreases. Furthermore, an increase in the number or area of the aluminum wiring connecting the gate electrode and the external terminal increases the area occupied by the preliminary isolation insulating film, reducing the degree of integration of the semiconductor device.

(4) In order to solve the above problems (1) to (3),
When the thickness of the aluminum wiring is increased, processing accuracy in the manufacturing process is reduced. A decrease in processing accuracy increases the pattern size of the aluminum wiring and increases the area occupied by the above-mentioned element isolation insulating film. Furthermore, a decrease in processing accuracy increases the pattern size of aluminum wiring and increases the arrangement pitch of insulated gate field effect transistors. Therefore, the degree of integration of the semiconductor device decreases.

An object of the present invention is to provide a technique that can improve the frequency characteristics of a transistor in a single-piece semiconductor device equipped with a transistor.

Another object of the present invention is to provide a technique that can improve the driving ability of a transistor in a single-piece semiconductor device equipped with a transistor.

Another object of the present invention is to provide a technique that can improve the degree of integration of transistors in a single-piece semiconductor device equipped with transistors.

Another object of the present invention is to meet any two of the above objects and other objects.
Our goal is to provide technology that allows us to achieve both at the same time.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) In a single structure semiconductor device in which a gate electrode and a source region of an insulated gate field effect transistor whose drain region is formed in a semiconductor substrate are each connected to an external terminal, the gate electrode of the insulated gate field effect transistor is connected to an external terminal. However, the first electrode has a smaller specific resistance value than this gate electrode.
A second metal wiring is connected to the first external terminal by a metal wiring, and the source region has a specific resistance value /h lower than that of the gate electrode and is formed in a conductive layer different from the first metal wiring. Connected to external terminal.

(2) The first metal wiring of the means (1) is formed in a conductive layer above the gate electrode of the insulated gate field effect transistor, and the second metal wiring is formed in a conductive layer above the first metal wiring. The first metal wiring has a thickness thinner than that of the second metal wiring.

(3) The first metal wiring of the means (1) or (2) is formed in a conductive layer above the gate electrode of the insulated gate field effect transistor along the gate electrode.

(4) The first metal wiring of the means (1) is formed in a conductive layer above the gate electrode of the insulated gate field effect transistor, and the second metal wiring is formed in a conductive layer above the gate electrode. The second metal wiring or the first metal wiring in the uppermost layer is configured to have a thicker film thickness than the first metal wiring or the second metal wiring in the lower layer. The second metal wiring or the first metal wiring in the uppermost layer constitutes the first external terminal and the second external terminal, respectively.

(5) The first external terminal and the second external terminal of the means (4) together occupy the entire surface of the semiconductor substrate.

[For production]

According to the above-mentioned means (1), the gate resistance value of the insulated gate field effect transistor can be reduced by the first metal wiring having a small specific resistance value, and the switching speed can be increased, so that the high frequency characteristics of the semiconductor device can be improved. At the same time, the source resistance value is reduced by the second metal wiring having a small specific resistance value,
Since the amount of current flowing between the source region and the drain region of the insulated gate field effect transistor can be increased, the driving ability of the semiconductor device can be improved.

According to the above-mentioned means (2), the processing precision of the first metal wiring can be increased, and the processing precision of the gate electrode of the insulated gate field effect transistor can be increased by the increased processing precision. The area occupied by the effect transistor can be reduced and the degree of integration of the semiconductor device can be improved.

According to the above-mentioned means (3), since the region below the first metal wiring is used as an active region and the first metal wiring is extended to the active region, the element isolation insulating film can be reduced. The degree of integration of the semiconductor device can be improved by an amount corresponding to the area occupied by the film.

According to the above-mentioned means (4), the first external terminal, the second
Each of the external terminals is configured with the thick second metal wiring or the first metal wiring in the uppermost layer, and damage or destruction to the lower parts of the first external terminal and the second external terminal can be reduced during bonding. The lower portions of each of the first external terminal and the second external terminal are used as active regions, and the degree of integration of the semiconductor device can be improved.

According to the above-mentioned means (5), bonding can be freely performed at either the periphery or the center on the surface of the semiconductor substrate, and the number of bonding locations can be freely set. A place where bonding is performed in the area! 111 B onding Pa
d on Active area).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to a single-structure semiconductor device (power transistor) equipped with an insulated gate field effect transistor.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Example ■) The schematic configuration of a single structure semiconductor device equipped with an insulated gate field effect transistor, which is Example I of the present invention, is shown in the second example.
This is shown in the figure (chip layout diagram).

As shown in FIG. 2, the single-piece semiconductor device [20 is composed of a semiconductor chip having a rectangular planar shape.

Although not limited to this size, a single structure semiconductor device 2
0 is composed of, for example, a rectangular semiconductor chip of 2 [mm] x 2 [mm].

This single structure semiconductor device 20 has a two-layer wiring structure. In other words, it is composed of a first layer of metal wiring 8 and a second layer of metal wiring 10 formed on a conductive layer above it. Each of the metal wirings 8 and 10 is made of aluminum or an aluminum alloy, which has a specific resistance value smaller than that of a gate material (polycrystalline silicon film), which will be described later.

The first layer of metal wiring 8 in the two-layer wiring structure is formed over almost the entire area within an effective area 14 surrounded by a buffer region 13, although details of its planar pattern will be described later. The effective area 14 is an active region in which insulated gate field effect transistors Q are arranged. The buffer region 13 is configured for the purpose of ensuring the withstand voltage of the insulated gate field effect transistor Q, especially the drain region. In addition, the buffer region 13 is used to protect the insulated gate field effect transistor Q when the end face of the semiconductor chip is damaged.
Constructed for purposes that do not affect the characteristics of the This buffer region 13 has, for example, a dimension of about 10[mu]m inward from the end surface of the semiconductor chip.

The first layer metal wiring 8 mainly constitutes a metal wiring 8G and a source electrode 8S connected to the gate electrode (6) of the insulated gate field effect transistor Q, respectively. The metal wiring 8G is connected to an external terminal (ponding pad) IOGP through an opening 9G formed in the glabellar insulating film (9). The external terminal 10GP is formed of the second layer metal wiring 10, and in the small area required for the external terminal 100P,
It occupies the planar area of the semiconductor device 20. External terminal 10G
A bonding wire 12 is connected to P through a bonding opening 11T formed in the final protective film (11).

The second layer metal wiring 10 in the two-layer wiring structure is formed over almost the entire effective area 14, although details of its planar pattern will be described later. The second layer metal wiring 10 is mainly a metal wiring 10S connected to the source region (4) of the insulated gate field effect transistor Q.
, constitutes the external terminal 108P and the external terminal 100P. The metal wiring 10S and the external terminal 108P are each formed on the same conductive layer and are integrally constructed. In other words, the metal wiring 10S occupies most of the planar area of the semiconductor device 20, excluding the area of the external terminal 100P, and
P is configured using a part of the metal wiring 10S.

The bonding wire 12 is connected to the external terminal 108P through the bonding opening 11T.

A plurality of insulated gate field effect transistors Q are regularly arranged within the effective transistor 14 of the semiconductor device 20 having a single structure. Regarding the structure of the insulated gate field effect transistor Q, FIG.
FIG. 4 (an enlarged plan view of the main part of the area surrounded by the symbol ■ in FIG. 2).

As shown in FIGS. 1 and 3, an insulated gate field effect transistor Q is formed on the main surface of an n-type semiconductor substrate 1 with a high impurity concentration. Specifically, the insulated gate field effect transistor Q is formed on the main surface of a low impurity concentration n-type epitaxial layer 2 grown on the main surface of a Go-type semiconductor substrate 1 . For example, the n-type semiconductor substrate 1 has a density of 400 to 500
The thickness is approximately [μm]. The n-type epitaxial layer 2 has a thickness of about 5 to 100 [μm].

This insulated gate field effect transistor Q is mainly composed of a channel forming region, a gate insulating film 5, a gate electrode 6, a source region, and a drain region.

The drain region is composed of an n-type epitaxial layer 2 and an n'-type semiconductor substrate 1. Although not shown, the drain region is connected to an external device via the back surface of the n-type semiconductor substrate 1 that faces the main surface.

The channel forming region is composed of a p-type semiconductor region 3 formed on the main surface of the n-type epitaxial layer 2 between the gate electrodes 6 .

The source region is composed of an n'-type semiconductor region 4 formed on the main surface of the p-type semiconductor region 3 on the side of the gate electrode 6.

Gate insulating film 5 is formed on the main surface of p-type semiconductor region 3, which is a channel forming region, between the source region and the drain region. The gate insulating film 5 is formed of, for example, a silicon oxide film.

A gate electrode 6 is formed on the gate insulating film 5. This gate electrode 6 is formed of a gate material, for example, a polycrystalline silicon film. As shown in FIG. 3, the gate electrode 6 has a planar shape having a mesh pattern (mesh pattern or lattice pattern),
It is arranged almost throughout the effective area 14. The n-type semiconductor region 4, which is the source region mentioned above, is formed on the main surface of the channel forming region within the region surrounded by the mesh pattern of the gate electrode 6.

For example, approximately tens of thousands of insulated gate field effect transistors Q configured in this manner are connected and arranged in parallel within the effective area 14 of the semiconductor device 20 having a single structure. In other words, as the number of insulated gate field effect transistors Q increases, the gate width per unit area can increase, and the amount of current that can flow between the source region and the drain region can be increased.

The gate electrode 6 of the insulated gate field effect transistor Q is a metal wiring 8G formed of the first layer metal wiring 8.
and is connected to the aforementioned external terminal 100P through this metal wiring 8G. The metal wiring 8G is the gate electrode 6
It is formed in the upper conductive layer of the gate electrode 6 , extends along the gate electrode 6 , and is electrically connected to the gate electrode 6 in a mesh pattern substantially similar to the mesh pattern of the gate electrode 6 . The gate electrode 6 and the metal wiring 8G are each connected to the interlayer insulating film 7.
This is done through the open lower G formed in . Open lower G is
As shown in FIG. 3, a plurality of them are arranged at a predetermined pitch in the extending direction of the gate electrode 6, or they are formed in the shape of elongated slits in the extending direction of the gate electrode 6, although not shown. In other words, the metal wiring 8G is configured as a backing wiring whose specific resistance value is smaller than that of the gate electrode 6. Therefore, metal wiring 8
Since the region below G is an active region in which the gate electrode 6 extends, basically no element isolation insulating film (field oxide film) is present. The interlayer insulating film 7 is formed of, for example, a polyimide resin film with good step coverage. The metal wiring 8G is formed to have a wiring width that is approximately the same as that of the gate electrode 6 or slightly smaller than that of the gate electrode 6 in order not to impair the arrangement pitch of the gate electrode 6. In addition, metal wiring 8G is
In order to improve processing accuracy, it is formed with a thin film thickness. For example, the metal wiring 8 is formed with a film thickness of about 1 μml.

The Go-type semiconductor region 4, which is the source region of the insulated gate field effect transistor Q, is connected to a source electrode 8S formed of a first layer of metal wiring 8. This source electrode 8
S is constituted by an island region having a rectangular planar shape within the region surrounded by the mesh pattern of the gate electrode 6. This source electrode 8S is connected to the source region through an open lower S formed in the interlayer insulating film 7. This source electrode 8S is the second
It is connected to the external terminal 105P through the metal wiring 10S formed of the metal wiring 10 of the second layer. The source electrode 8S and the metal wiring 10S are connected through an opening 9S formed in the glabella insulating film 9. The interlayer insulating film 9 is formed of a polyimide resin film similarly to the glabellar insulating film 7 described above. The opening 9S is formed for each of the plurality of source electrodes 8S. As described above, the metal wiring 10S is formed throughout the effective area 14 except for the areas of the external terminals 100P and 105P. The metal wiring 10S is formed with a thick film thickness that reduces the source resistance value and does not damage the underlying layer or the insulated gate field effect transistor Q during bonding. For example, the metal wiring 10S is 3.5 to 5°0[
It is formed with a film thickness of about μml.

The final protective film 11 formed on the upper layer of the second layer metal wiring 10 is formed of, for example, a polyimide resin film.

In this way, (1) the gate electrode 6 and the source region (n'' type semiconductor region 4) of the insulated gate field effect transistor Q whose drain region is formed using the n'' type semiconductor substrate 1 (and the n type epitaxial layer 2) are Each has 100 external terminals
, a single structure semiconductor device 2 connected to IO8P
0, the insulated gate field effect transistor Q
The gate electrode 6 is connected to the external terminal 100P by a metal wiring 8G having a smaller specific resistance value than the gate electrode 6, and the source region (4) has a smaller specific resistance value than the gate electrode 6. Further, it is connected to an external terminal 108P by a metal wiring 10S formed in a conductive layer different from that of the metal wiring 8G.

With this configuration, the metal wiring 80P having a small specific resistance value
Since the gate resistance value of the insulated gate field effect transistor Q can be reduced and the switching speed can be increased, the high frequency characteristics of the single structure semiconductor device 20 can be improved. Since the amount of current flowing between the source region and the drain region of the insulated gate field effect transistor Q can be increased, the driving ability of the semiconductor device 20 having a single structure can be improved.

(2) The metal wiring 8G of the structure (1) is formed in a conductive layer above the gate electrode 6 of the insulated gate field effect transistor Q, and the metal wiring 10S is formed in a conductive layer above the metal wiring 8G. The metal wiring 8G has a thinner film thickness than the metal wiring 10S. With this configuration, the processing precision of the metal wiring 8G can be increased, and the processing precision of the gate electrode 6 of the insulated gate field effect transistor Q can be increased by the increased processing precision. Reduce area,
The degree of integration of the semiconductor device 20 having a single structure can be improved.

(3) Metal wiring 8G of the above configuration (1) or (2)
is formed along the conductive layer above the gate electrode 6 of the insulated gate field effect transistor Q. With this configuration, the region below the metal wiring 8G is used as an active region, and the metal wiring 8G is extended to the active region),
Since the element isolation insulating film can be reduced, the degree of integration of the single structure semiconductor device 20 can be improved by an amount corresponding to the area occupied by the element isolation insulating film.

(4) The metal wiring 8G of the structure (1) is formed in a conductive layer above the gate electrode 6 of the insulated gate field effect transistor Q, and the metal wiring 10S is formed in a conductive layer above the gate electrode 6. This uppermost layer metal wiring 10S is configured with a thicker film thickness than the lower layer metal wiring 8G, and this uppermost layer metal wiring 10S connects the external terminals LOG P, It constitutes each of the 10SPs.

With this configuration, the external terminals LOGP, IO8
Each of P is constituted by a thick metal wiring 10 in the uppermost layer,
External terminal LOG P, 105 P during bonding
Since damage and destruction of the lower portions of the external terminals 100P and 108P can be reduced, the lower portions of the external terminals 100P and 108P can be used as active regions, and an insulated gate field effect transistor Q can be mounted, thereby improving the degree of integration of the semiconductor device 20 having a single structure. can.

Also, (5) the external terminal 10GP of the configuration (4).

Each of the 10 SPs collectively covers the effective area 14 of the semiconductor substrate 1.
occupies the entire surface of the With this configuration, the semiconductor substrate 1
Since bonding can be freely performed at either the peripheral or central position on the surface of the active region, and the number of bonding locations can be freely set, the so-called BPA (Bonding Pad
n Active area).

(Example ■) In this example ■, in the above-mentioned single-piece structure semiconductor device,
This is a second embodiment of the present invention in which the layers of the metal wiring connected to the gate electrode and the metal wiring connected to the source region of an insulated gate field effect transistor are exchanged.

FIGS. 5 and 6 (enlarged plan views of the main parts) show the structure of the main parts of a single-piece structure semiconductor device equipped with an insulated gate field effect transistor, which is Embodiment (2) of the present invention.

As shown in FIGS. 5 and 6, the single structure semiconductor device 20 of this embodiment Second layer metal wiring 1 with gate electrode 8G interposed
The metal wiring 10G formed by 0 is connected. The metal gate electrode 8G is formed in an island shape, the metal wiring 10G is formed throughout the effective area 14, and the external terminal 10
Connected to GP. A mesh pattern metal wiring 8S formed of the first layer metal wiring 8 is connected to the n-type semiconductor region 4 which is the source region. Metal wiring 8S is external terminal 10
Connected to 8P.

The semiconductor device 20 having a unitary structure configured in this way can produce substantially the same effects as in the embodiment (2).

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention can be applied to a single-structure semiconductor device equipped with an insulated gate field effect transistor whose drain region is a p-type semiconductor substrate.

Further, the present invention can be applied to a single-structure semiconductor device equipped with a bipolar transistor whose collector region is a semiconductor substrate. In this case, for example, the present invention connects the emitter region to the first layer metal interconnect via the first layer metal interconnect or the emitter electrode formed of the polycrystalline silicon film, and connects the base region to the second layer metal interconnect. Connect to the metal wire of the eye.

Further, in the present invention, a single-piece semiconductor device may be configured with a multilayer metal wiring structure of three or more layers.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a single-piece semiconductor device equipped with a transistor, frequency characteristics of the transistor can be improved.

Furthermore, in a single-piece semiconductor device equipped with a transistor, the driving ability of the transistor can be improved.

Further, in a single-piece semiconductor device equipped with a transistor, the degree of integration of the transistor can be improved.

Moreover, any two of the above effects can be achieved at the same time.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device with a single structure equipped with an insulated gate field effect transistor according to Embodiment I of the present invention, FIG. 2 is a chip layout diagram of the semiconductor device with a single structure, and FIG. 3 and 4 are enlarged plan views of essential parts of the insulated gate field effect transistor, and FIGS. 5 and 6 show a single structure mounted with an insulated gate field effect transistor according to the embodiment (2) of the present invention. FIG. 2 is an enlarged plan view of a main part of the semiconductor device of FIG. In the figure, 1... semiconductor substrate, 2... epitaxial layer (drain region), 3... p-type semiconductor region (channel formation region), 4... n-type semiconductor region (source region)
, 6... Gate electrode, 8.8G, 8S... First layer metal wiring, 10. LOG, IO8...second layer metal wiring, 10GP, 10SP...external terminal, Q...insulated gate field effect transistor.

Claims (1)

[Scope of Claims] 1. In a single-structure semiconductor device in which a gate electrode and a source region of an insulated gate field effect transistor whose drain region is formed in a semiconductor substrate are each connected to an external terminal, the insulated gate field effect transistor A gate electrode of the effect transistor is connected to a first external terminal by a first metal wiring having a resistivity smaller than that of the gate electrode, and a source region is connected to the first external terminal by a first metal wiring having a resistivity smaller than that of the gate electrode. 1
A semiconductor device characterized in that the semiconductor device is connected to a second external terminal by a second metal wiring formed in a conductive layer different from the metal wiring. 2. The first metal wiring is formed in a conductive layer above the gate electrode of the insulated gate field effect transistor, and the second metal wiring is formed in a conductive layer above the first metal wiring. 2. The semiconductor device according to claim 1, wherein the wiring has a thickness thinner than that of the second metal wiring. 3. The semiconductor device according to claim 1 or 2, wherein the first metal wiring is formed in a conductive layer above the gate electrode of the insulated gate field effect transistor along the gate electrode. . 4. The first metal wiring is a conductive layer above the gate electrode of the insulated gate field effect transistor, and the second metal wiring is a conductive layer above the gate electrode and the first metal wiring. or a lower conductive layer, and the second metal wiring or the first metal wiring in the uppermost layer has a thicker film thickness than the first metal wiring or the second metal wiring in the lower layer; 2. The semiconductor device according to claim 1, wherein each of the first external terminal and the second external terminal is formed of a two-metal wiring or a first metal wiring. 5. The semiconductor device according to claim 4, wherein each of the first external terminal and the second external terminal collectively occupies the entire surface of the semiconductor substrate.