JPH043991A - Formation of wiring conductor of thick film integrated circuit - Google Patents
Formation of wiring conductor of thick film integrated circuitInfo
- Publication number
- JPH043991A JPH043991A JP10505390A JP10505390A JPH043991A JP H043991 A JPH043991 A JP H043991A JP 10505390 A JP10505390 A JP 10505390A JP 10505390 A JP10505390 A JP 10505390A JP H043991 A JPH043991 A JP H043991A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- paste
- layer
- conductor layer
- wiring conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 title claims abstract description 89
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000007772 electroless plating Methods 0.000 claims abstract description 6
- 150000002736 metal compounds Chemical class 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052802 copper Inorganic materials 0.000 abstract description 5
- 239000010949 copper Substances 0.000 abstract description 5
- 238000010304 firing Methods 0.000 abstract description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 4
- 238000007639 printing Methods 0.000 abstract description 4
- 229910052759 nickel Inorganic materials 0.000 abstract description 2
- 238000007650 screen-printing Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 39
- 239000010408 film Substances 0.000 description 10
- 238000007747 plating Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000003054 catalyst Substances 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 150000002902 organometallic compounds Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、厚膜集積回路の配線パターンの複合導体化
に用いられる、厚膜集積回路の配線導体の形成方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming a wiring conductor for a thick film integrated circuit, which is used for forming a wiring pattern of a thick film integrated circuit into a composite conductor.
従来、厚膜集積回路では、基板の表面に下層導体を成す
導体ペーストとしてAgペーストやAg・Pdペースト
を用いて、回路パターンを印刷によって形成し、その上
に上層導体として銅メッキ処理を施し、上層導体の下地
となる下層導体とその表面上の上層導体との複合化によ
り配線導体の低インピーダンス化が図られている。Conventionally, in thick film integrated circuits, a circuit pattern is formed by printing on the surface of a substrate using Ag paste or Ag/Pd paste as a conductor paste forming a lower layer conductor, and then copper plating is applied to the upper layer conductor. The impedance of the wiring conductor is reduced by combining the lower layer conductor, which is the base of the upper layer conductor, and the upper layer conductor on the surface of the lower layer conductor.
ところで、このような配線導体の複合化処理は、複合導
体によって低インピーダンス化を図ることに他ならない
が、上層導体の下地即ち、下層導体は上層導体を設置す
るための基板に対する接着手段としての機能を持つもの
である。即ち、基板上に銅メッキを直接行うことができ
れば、下層導体は不要になるといっても過言ではないし
、上層導体が銅である場合、配線導体の低インピーダン
ス化は上層導体で確保されることになる。By the way, such a composite wiring conductor process is nothing but an attempt to reduce impedance by using a composite conductor, but the lower layer conductor, which is the base for the upper layer conductor, functions as a bonding means to the board on which the upper layer conductor is installed. It is something that has. In other words, it is no exaggeration to say that if copper plating can be performed directly on the board, there will be no need for a lower layer conductor, and if the upper layer conductor is copper, the lower impedance of the wiring conductor will be ensured by the upper layer conductor. Become.
そこで、この発明は、下層導体の膜厚を薄く形成して上
層導体を形成し、低インピーダンス化を図ることができ
る厚膜集積回路の配線導体の形成方法の提供を目的とす
る。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for forming a wiring conductor for a thick film integrated circuit, in which a lower layer conductor is formed thinner to form an upper layer conductor, thereby achieving lower impedance.
即ち、この発明の厚膜集積回路の配線導体の形成力法は
、基板(2)の表面に回路パターンを有機金属化合物を
含む導体ペースト(レジネートペースト4)で形成し、
この導体ペーストを焼成して第1の導体層(40)を形
成した後、この第1の導体層の上に無電解メッキ処理に
よって第2の導体層(6)を形成することを特徴とする
。That is, the method of forming a wiring conductor for a thick film integrated circuit according to the present invention involves forming a circuit pattern on the surface of a substrate (2) using a conductor paste (resinate paste 4) containing an organometallic compound;
After the conductor paste is fired to form the first conductor layer (40), the second conductor layer (6) is formed on the first conductor layer by electroless plating. .
第2の導体層を無電解メッキ処理で形成する場合、下層
導体である第1の導体層は、第2の導体層のメッキ処理
に際し、触媒的作用を果たすことになる。したがって、
第1の導体層は膜厚を厚くする必要はなく、第2の導体
層が設置できる条件を備えればよい。When the second conductor layer is formed by electroless plating, the first conductor layer, which is the lower conductor, acts as a catalyst during the plating of the second conductor layer. therefore,
The first conductor layer does not need to be thick; it is sufficient to provide conditions that allow the second conductor layer to be installed.
そこで、第1の導体層に有機金属化合物を含む導体ペー
ストを用いれば、その焼成後、従来の導体ペーストに比
較して金属密度が高くなるとともに膜厚を薄く形成でき
、メッキを形成する際に触媒としての働きが高くなり、
メッキ層の析出がし易くなる。したがって、有機金属化
合物を含む導体ペーストで形成された第1の導体層の上
に第2の導体層を無電解メッキ処理によって形成すれば
、第1及び第2の導体層から成る複合導体が容易に形成
され、従来のような貴金属から成る導体ペーストの使用
量が削減できるとともに、配線導体の低インピーダンス
化が実現され、信軌性の高い回路パターンが得られる。Therefore, if a conductor paste containing an organic metal compound is used for the first conductor layer, after firing, the metal density will be higher than that of conventional conductor pastes, and the film thickness will be thinner. It works better as a catalyst,
Precipitation of the plating layer becomes easier. Therefore, if a second conductor layer is formed by electroless plating on a first conductor layer formed of a conductor paste containing an organometallic compound, a composite conductor consisting of the first and second conductor layers can be easily formed. This reduces the amount of conductive paste made of conventional noble metals, and also reduces the impedance of the wiring conductor, resulting in a circuit pattern with high reliability.
以下、この発明を図面に示した実施例を参照して詳細に
説明する。Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.
第1図は、この発明の厚膜集積回路の配線導体の形成方
法の一実施例を示す。FIG. 1 shows an embodiment of the method for forming a wiring conductor for a thick film integrated circuit according to the present invention.
第1図の(A)に示すように、アルミナ磁器等の絶縁性
材料を以て平坦な基板2を形成する。As shown in FIG. 1A, a flat substrate 2 is formed of an insulating material such as alumina porcelain.
次に、この基板2の表面に第1図の(B)に示すように
、有機金属化合物を含む導体ペースト、即ち、レジネー
トペースト4を以て回路パターンをスクリーン印刷等に
より形成する。Next, as shown in FIG. 1B, a circuit pattern is formed on the surface of the substrate 2 using a conductor paste containing an organic metal compound, that is, a resinate paste 4, by screen printing or the like.
次に、このレジネートペースト4を焼成し、第1図の(
C)に示すように、第1の導体層40を形成する。レジ
ネートペースト4を焼成すると、その焼成により、レジ
ネートペースト4中の有機鎖が抜けるため、レジネート
ペースト4によって得られた導体層40の膜厚は、印刷
時、レジネートペースト4が持つ膜厚の1/10以下に
なる。Next, this resinate paste 4 is fired, and it becomes (
As shown in C), a first conductor layer 40 is formed. When the resinate paste 4 is fired, the organic chains in the resinate paste 4 are removed due to the firing, so that the thickness of the conductor layer 40 obtained by the resinate paste 4 is 1/1 of the thickness of the resinate paste 4 during printing. Becomes 10 or less.
次に、導体層40の上に無電解メッキ処理により、銅、
ニッケル等の導体をメッキし、第1図の(D)に示すよ
うに、第2の導体層6を形成する。Next, copper,
A conductor such as nickel is plated to form a second conductor layer 6 as shown in FIG. 1(D).
この結果、導体層40.6から成る配線導体8が形成さ
れる。As a result, wiring conductor 8 consisting of conductor layer 40.6 is formed.
このような形成方法によって得られた配線導体8は、第
2図に示すように、下層導体としての導体層40が持つ
抵抗r1と、上層導体としての導体層6が持つ抵抗r2
との並列回路を成し、配線導体8の持つ抵抗rは、r、
・rz/(r+ 十rz)となり、その大小関係は、r
<r、、r<r2であるから、その低インピーダンス化
が図られる。As shown in FIG. 2, the wiring conductor 8 obtained by such a formation method has a resistance r1 of the conductor layer 40 as a lower layer conductor and a resistance r2 of the conductor layer 6 as an upper layer conductor.
The resistance r of the wiring conductor 8 is r,
・rz/(r+10rz), and the magnitude relationship is r
Since <r, , r<r2, the impedance can be reduced.
そして、レジネートペースト4を用いた場合には、従来
の導体ペーストに比較して焼成処理後の金属密度が高く
なるので、メッキを形成する際に触媒としての働きが高
くなり、メッキ層の析出がし易い等、極めて有効であり
、しかも、膜厚を薄くできるので、金属使用量が削減で
き、製造コストの低減とともに、配線導体8の全体の膜
厚の低減をも図ることができる。このように、膜厚を薄
く形成した配線導体8では、低インピーダンス化に加え
、半田を付着させた場合の半田量われやマイグレーショ
ン等の不都合を防止することができる。When Resinate Paste 4 is used, the metal density after firing is higher than that of conventional conductor pastes, so it acts more as a catalyst when forming plating, and prevents the precipitation of the plating layer. It is extremely effective as it is easy to fabricate, and moreover, since the film thickness can be reduced, the amount of metal used can be reduced, manufacturing costs can be reduced, and the overall film thickness of the wiring conductor 8 can be reduced. In this way, the wiring conductor 8 formed with a thin film thickness can not only lower impedance but also prevent problems such as solder cracking and migration when solder is attached.
また、レジネートペースト4の印刷には、従来の導体ペ
ーストと同様の印刷方法を用いることができ、レジネー
トペースト4を用いることによる設備の変更等を伴うこ
とがない。Furthermore, the resinate paste 4 can be printed using a printing method similar to that used for conventional conductor pastes, and the use of the resinate paste 4 does not require changes to equipment.
以上説明したように、この発明によれば、配線導体の低
インピーダンス化とともに、金属使用量の削減で製造コ
ストの低減を図ることができ、有機金属化合物を含む導
体ペーストとしてレジネートペーストを用いれば、焼成
処理後、従来の導体ペーストに比較して金属密度が高く
なるので、メッキを形成する際に触媒としての働きが高
く、メンキ層の析出がし易い等、回路パターンの信頼性
を高めることができる。As explained above, according to the present invention, it is possible to reduce the impedance of the wiring conductor and reduce the manufacturing cost by reducing the amount of metal used. If resin paste is used as the conductor paste containing an organometallic compound, After the firing process, the metal density is higher than that of conventional conductor paste, so it acts as a catalyst when forming plating, making it easier to deposit a coating layer, thereby increasing the reliability of the circuit pattern. can.
第1図はこの発明の厚膜集積回路の配線導体の形成方法
の一実施例を示す図、
第2図は第1図に示した配線導体の等価回路を示す図で
ある。
2・・・基板
4・・・レジネートペースト(有機金属化合物を含む導
体ペースト)
6・・・第2の導体層
8・・・配線導体
40・・・第1の導体層
レノ不
第1の導体層
船FIG. 1 is a diagram showing an embodiment of the method of forming a wiring conductor for a thick film integrated circuit according to the present invention, and FIG. 2 is a diagram showing an equivalent circuit of the wiring conductor shown in FIG. 1. 2... Substrate 4... Resinate paste (conductor paste containing an organic metal compound) 6... Second conductor layer 8... Wiring conductor 40... First conductor layer non-first conductor layer ship
Claims (1)
体ペーストで形成し、この導体ペーストを焼成して第1
の導体層を形成した後、この第1の導体層の上に無電解
メッキ処理によって第2の導体層を形成することを特徴
とする厚膜集積回路の配線導体の形成方法。A circuit pattern is formed on the surface of the substrate using a conductor paste containing an organic metal compound, and this conductor paste is fired to form the first
1. A method for forming a wiring conductor for a thick film integrated circuit, the method comprising forming a second conductor layer on the first conductor layer by electroless plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10505390A JPH043991A (en) | 1990-04-20 | 1990-04-20 | Formation of wiring conductor of thick film integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10505390A JPH043991A (en) | 1990-04-20 | 1990-04-20 | Formation of wiring conductor of thick film integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH043991A true JPH043991A (en) | 1992-01-08 |
Family
ID=14397246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10505390A Pending JPH043991A (en) | 1990-04-20 | 1990-04-20 | Formation of wiring conductor of thick film integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH043991A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005174828A (en) * | 2003-12-12 | 2005-06-30 | Hitachi Ltd | Wiring conductor forming composition, wiring board manufacturing method using the same, and wiring board |
-
1990
- 1990-04-20 JP JP10505390A patent/JPH043991A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005174828A (en) * | 2003-12-12 | 2005-06-30 | Hitachi Ltd | Wiring conductor forming composition, wiring board manufacturing method using the same, and wiring board |
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