JPH0439947A - Method of marking semiconductor chip - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor chip marking method for writing a mark such as a defective mark or an identification code on a semiconductor chip.

[Conventional technology]

A semiconductor chip used in a conventional semiconductor device is manufactured as follows. Active elements such as transistors, diodes,
A plurality of passive elements such as capacitors and coils, wiring connecting these elements, and electrode pads for connection to external terminals are repeatedly formed. Next, a probe is brought into contact with the electrode pads on the semiconductor wafer to electrically inspect whether the elements are fabricated as designed. that time,
A defective mark is added to a failed element. after that,
The semiconductor wafer is divided into semiconductor chips through a scribing process. The defective marked chips are removed by a visual inspection or other sorting method to complete the semiconductor chip.

Conventionally, methods for adding the defective marks include applying marking ink containing iron oxide or pattern burning using a laser beam.

[Problem to be solved by the invention]

Conventional marking methods for semiconductor chips are formed as described above, so it is difficult to control the amount of marking ink, and if there is too much marking ink, the marking ink may spread and adhere to adjacent non-defective semiconductor patterns, or the ink may "drip". ” may adhere to good semiconductor patterns, causing problems such as erroneous judgments during sorting after the scribing process and a decrease in retention. In addition, the method using a laser beam requires expensive equipment and has problems such as molten metal scattering during burnout and adhering to non-defective semiconductor patterns.

This invention was made to solve the above-mentioned problems, and it is possible to accurately mark pass/fail marks or fail marks on semiconductor chips without using liquid materials such as ink or requiring expensive equipment such as lasers. The object of the present invention is to obtain a marking method for semiconductor chips that can write an identification mark.

[Means to solve the problem]

The semiconductor chip marking method according to the present invention utilizes the fact that the intermetallic compound has a different color from the single or alloyed metal that forms the intermetallic compound, and forms the intermetallic compound on the semiconductor chip. This is a multilayer structure in which two or more types of metals and a metal layer (barrier layer) separating these metal layers are formed.

[Effect]

The method for marking semiconductor chips and knobs in this invention involves applying pressure to the multilayer metal layer from the outside, destroying the barrier layer, and bringing the metal layers that form intermetallic compounds into direct contact. The added area forms an intermetallic compound and changes color to a different color from other areas, making it possible to identify the presence or absence of the mark from the color tone.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a cross-sectional view of a semiconductor chip that is an embodiment of the present invention.
FIG. 2 is a process cross-sectional view schematically showing the principle by which marking is possible in the metal layer of the semiconductor chip in FIG. 1. In the figure, 1 to 3 are metal thin film layers; indicates a semiconductor chip (wafer), metal layer 1 and metal layer 3 are metal thin films that form an intermetallic compound, and metal layer 2 is a metal layer for separating metal layer 1 and metal layer 3.0 For example, metal layer 1 is aluminum (A1), metal layer 3 is (Au
).

Metal layer 2 is made of molybdenum (MO).

Next, the marking process will be explained using FIG. 2. First, in Figure I81, 5 is a marking jig, and when it is determined that the semiconductor chip 7 (or semiconductor wafer part) requires marking, the jig 5 is used as shown in Figure b1. Contact pressure is applied to the metal layer. Then, a part of the jig 5 bites into the metal layer, destroying the metal layer 2, and the metal layer 1
and the metal layer 3 are in direct contact with each other. Thereafter, by carrying out a heat treatment, metal 1 and gold [3 are alloyed as shown in the Fe2 diagram, and an intermetallic compound is formed as shown in part 6 of the figure.

For example, in the metal layer mentioned above, Au and AI easily react at temperatures above 200°C, and AI! ALI, AlAu, Al
Intermetallic compounds such as AlI2, AlAu, AlAu3, etc. are formed, and these have a different color tone, such as purple, from the outermost layer A1, making it easy to identify whether or not pressure has been applied.

In the above embodiment, the case where the multilayer metal layer is three layers is shown, but three or more metal layers may also be used.
Although XN is formed exclusively, it may be used in combination with an external electrode.

In addition, as a similar prior art method, a large current is applied to cause Au and A1 to react, and marking is performed based on the uneven color tone of the surface (pending application, semiconductor device, filed on November 21, 1986, inventor: Masao Sumiyoshi, Mitsubishi Electric). Co., Ltd.), but this conventional example requires a large power source because it uses an electric current for the reaction.
Further, there are problems such as wear due to burnout of the probe, but the method of the present invention requires only pressurization and heating, and marking can be done at low cost and with good reproducibility.

Note that the marking method of the above embodiment is applicable not only to defect marks but also to classification marking when classifying electrical characteristics such as hFE+gn of a plurality of semiconductor patterns formed on a semiconductor wafer. The function of the jig 5 may be added to the probe that contacts the upper electrode and evaluates the electrical characteristics.

〔Effect of the invention〕

As described above, according to the present invention, since no ink is used, there are no problems such as ink spreading or dripping, and it is possible to easily mark even minute parts, and the device is also better than laser methods etc. It has the advantage that it can be realized at low cost.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor chip according to an embodiment of the present invention, and FIG. 2 is a process sectional view illustrating a marking method using the multilayer metal layer of FIG. In the figure, 1, 2. 3 is a multilayer metal layer, 1°3 is a metal layer forming an intermetallic compound, and 2 is a barrier layer. 4
5 represents a semiconductor wafer, 5 represents a marking jig, and 6 represents an alloy layer. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Hiri 1 and Toeba Figure 2 agent Masuo Oiwa. 3゜Procedural amendment (spontaneous) Relationship with the case dated September 29, 1990 by the person amending the indicated patent application No. 148193 Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name ( 601) Moriya Shiki, representative of Mitsubishi Electric Corporation 5, detailed description of the invention in the specification subject to amendment. Contents of the amendment (1) In the 4th line of page 3 of the specification, ``E. 2) In the specification, page 6, line 12, ``Electrical characteristics of hFE, gn, etc.'' is corrected to ``Electrical characteristics of 7hpi9gm, etc.''. 4. Proxy address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo

Claims (1)

[Claims] Forming a laminated metal layer of three or more layers having first and second metal layers forming an intermetallic compound on a semiconductor wafer or semiconductor chip, and another third metal layer interposed between the metal layers,
By destroying the third metal layer by pressure or the like and directly connecting the first and second metal layers to form an intermetallic compound,
A method for marking semiconductor chips, which is characterized in that it enables identification.