JPH0440106A - Gain flattening circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a gain flattening circuit that is connected between high frequency circuits and flattens the gain of a high frequency signal.

[Prior Art] Various radio wave receivers used in satellite communication equipment, television tuners, etc. have built-in gain flattening circuits to reduce the frequency dependence of signal strength and ensure stable reception conditions. . Generally, active elements such as transistors and FETs used for signal amplification attenuate signals in high frequency regions (hereinafter referred to as high frequencies), so a high-pass type gain flattening circuit is often required. This gain flattening circuit is inserted, for example, between a mixing circuit and an intermediate frequency amplification circuit, or between an input circuit and a high frequency amplification circuit.

As the gain flattening circuit, for example, a high-pass filter as shown in FIG. 5 can be used. In the same figure, C1, C2, C3 are capacitors, LL, L2
is an inductor. In this high-pass filter, gain flattening within the desired band is achieved by C1, C2, C3, LL,
This is done by adjusting the value of L2. By this adjustment, the frequency characteristics of the insertion loss in the transition region between the rejection band and the passband of the high-pass filter are offset by the gain reduction in the high frequency range, and are flattened. In other words, the C
The values of 1, C2, C3, LL, and L2 are adjusted.

At that time, in order for gain flattening to occur smoothly,
It is desirable that the input/output impedance of this gain flattening circuit does not change due to variations in C1, C2, C3, LL, and L2. This is because if the input/output impedance changes due to fluctuations in the capacitors and inductance of these passive elements, the impedance of the circuits connected before and after this gain flattening circuit will change, and the reflection loss will also change. This is because desired gain flattening characteristics cannot be achieved simply by adjusting the transfer characteristics of the gain flattening circuit.

[Problems to be Solved by the Invention] However, in a gain flattening circuit using passive elements such as the conventional example described above, insertion loss is more or less caused by reflection loss. Furthermore, when a circuit is constructed using only passive elements, all insertion loss is reflection loss. That is, if C1, C2, C3°LL, L2 are changed, the input/output impedance of the gain flattening circuit will also change.

Therefore, in order to obtain the desired gain flattening characteristics, it is necessary to consider not only the transfer characteristics of the gain flattening circuit, but also the reflection loss that occurs between the circuits connected before and after the gain flattening circuit. , the problem arises that the adjustment becomes complicated and difficult.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a gain flattening circuit that can significantly reduce the labor required for circuit adjustment in gain flattening adjustment.

[Means for Solving the Problems] A gain flattening circuit according to the present invention for achieving the above object includes: a field effect transistor having a drain, a source, and at least one gate; and at least one of the field effect transistors. an input terminal connected to one gate; an output terminal connected to the drain of the field effect transistor; a parallel negative feedback circuit connected between the input terminal and the output terminal; and a source of the field effect transistor. and a series negative feedback circuit having a capacitor connected between the power source and the ground power source.

[Function] In the present invention having the above configuration, when the frequency of the signal from the input terminal becomes high and the output of the field effect transistor becomes small,
The feedback capacitance applied from the output terminal to the input terminal through the parallel negative feedback circuit is reduced, and a reduction in output is suppressed.

Gain flattening is thereby achieved. Furthermore, as the frequency becomes higher, the impedance of the capacitor of the series negative feedback circuit becomes smaller, and the amount of series non-feedback becomes smaller, thereby reducing the insertion loss in the high frequency range. Furthermore, the input/output impedance of this gain flattening circuit is approximately determined by the gate-source capacitance of the field effect transistor, and the output impedance is determined by the drain conductance of the field effect transistor as long as the field effect transistor is operated in the saturation region. Since it is almost determined by , it is almost unaffected by changes in the impedance of the series non-feedback circuit. Therefore, there is no need to consider variations in input/output impedance when adjusting the pass characteristics of the gain flattening circuit.

[Example] Hereinafter, a gain flattening circuit according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In the figure, the gain flattening circuit has an input terminal 1, an output terminal 2, a gate 4 connected to the input terminal 1, and an output terminal 2.
, a parallel negative feedback circuit 7 connected in parallel between the input terminal 1 and the output terminal 2, and the source 6 of the field effect transistor 3.
A series negative feedback circuit 8 connected between the
including.

In addition, v. , ) is a DC power supply and is connected to the drain 5 of the field effect transistor 3 via the coil L. The parallel negative feedback circuit 7 is a circuit in which a resistor Rp for adjusting the amount of parallel feedback and a capacitor Cp for blocking a direct current component are connected in series.

The series negative feedback circuit 8 includes a resistor Rs for adjusting the DC bias and a capacitor C for adjusting the amount of series feedback.
s are connected in parallel.

Next, the frequency characteristics of the gain flattening circuit shown in FIG. 1 will be explained.

The frequency dependence of the transfer characteristic in the gain flattening circuit configured as described above is determined by the frequency characteristics of the parallel negative feedback circuit 7, the series negative feedback circuit 8, and the field effect transistor 3 itself.

The parallel negative feedback circuit 7 suppresses the tendency of the field effect transistor 3 to reduce its gain in the high frequency range. That is, when the frequency is low, the amplification factor of the field effect transistor 3 does not vary, and the gain is limited to a constant value based on the amount of feedback returning from the drain 5 to the gate 4 through the resistor Rp. but,
As the frequency increases, the amplification factor of the field effect transistor 3 decreases, the amount of feedback decreases, and the tendency for gain to decrease in high frequencies is suppressed.

Further, as the frequency becomes higher, the impedance of the capacitor Cs of the series negative feedback circuit 7 becomes smaller, and the amount of series negative feedback becomes smaller. Therefore, insertion loss in the high frequency range of the gain flattening circuit can be reduced.

As described above, in the region where the frequency increases and the amplification factor of the field effect transistor 3 decreases, the amount of feedback by the resistor Rp of the parallel negative feedback circuit 7 becomes small, flattening the gain, and increasing the The amount of feedback due to Cs becomes small and can be reduced due to insertion loss.

Furthermore, fluctuations in input and output impedance of this gain flattening circuit will be explained. The input impedance of the field effect transistor is determined by the gate-source capacitance and is approximately constant, so the input impedance of the gain flattening circuit is not affected by changes in the impedance of the capacitor Cs. Further, since the output impedance of the field effect transistor 3 is almost determined by the drain conductance, the output impedance of the gain flattening circuit also hardly changes. That is, the input/output impedance of the present gain flattening circuit is not affected by the change in the capacitance of the capacitor Cs of the series negative feedback circuit 8, and the gain flattening and the pass characteristic are simply adjusted by adjusting the resistor Rp1 and the capacitor Cs. This eliminates the need to adjust the degree of interference matching between the circuits connected before and after the present gain flattening circuit.

FIG. 2 is a diagram showing measurement results of insertion loss and input/output return loss of the gain flattening circuit in the above embodiment. The field effect transistor 3 used here is shown as an equivalent circuit in FIG. 3, and the values of each circuit element of the parallel non-feedback circuit 7 and the series non-feedback circuit 8 are as follows: Rp=100Ω Cp=1000pF Rs=30Ω Yes, Cs is changed to 1.2.3.4.5 pF.

As shown in the characteristic diagram of FIG. 2, it can be seen that by increasing the capacitor Cs in FIG. 1, the high-pass frequency slope of the insertion loss can be varied continuously. Further, the input/output return loss hardly changes even when C8 is changed, and it can be seen that by using this gain flattening circuit, there is no need to adjust the degree of impedance matching with the preceding and following circuits.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

Referring to the figure, the difference from the embodiment in FIG. The point is that a field effect transistor 9 is provided.

Also in this second embodiment, by reducing the resistance Rp of the parallel negative feedback circuit 7 and increasing the amount of negative feedback, the frequency characteristics of the field effect transistors 3 and 9 can be suppressed, and by adjusting the capacitor Cs. , desired gain flattening can be performed without changing the input/output impedance of the gain flattening circuit. In addition, this embodiment has the advantage that by changing the bias voltage applied to the gate of the field effect transistor 9, it is possible to adjust the absolute value of the gain.

In the embodiment shown in FIG. 4, two field effect transistors are connected in series, but a so-called dual gate field effect transistor may be used instead. Further, the field effect transistor 9 may be replaced with a resistor. Further, the capacitor Cs used in the first and second embodiments may be adjusted by replacing fixed capacitance elements, or the capacitance may be adjusted by using a variable capacitance element such as a varactor diode.

[Effects of the Invention] As described above, in the present invention, since there is almost no change in input/output impedance due to change in transfer characteristics, the reflection loss between the circuits connected before and after the gain flattening circuit is kept constant. Gain flattening can be achieved simply by adjusting the feedback capacitance of the parallel negative feedback circuit and the series negative feedback circuit, resulting in the effect that the effort required for circuit adjustment can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing frequency characteristics of insertion loss and input/output return loss of the embodiment of FIG. 1, and FIG. 3 is a field effect transistor 3.
FIG. 4 is a circuit diagram showing a second embodiment of the present invention, and FIG. 5 is a circuit diagram showing a conventional example. In the figure, 1 is an input terminal, 2 is an output terminal, 3 is a field effect transistor, 4 is a gate, 5 is a drain, 6 is a source, 7 is a parallel negative feedback circuit, and 8 is a direct current. In the column feedback circuit, 9 is a field effect transistor, 10 is a gate, and 11 is a drain.

Claims (1)

[Claims] A field effect transistor having a drain, a source, and at least one gate; an input terminal connected to at least one gate of the field effect transistor; and an input terminal connected to the drain of the field effect transistor. a parallel negative feedback circuit connected between the input terminal and the output terminal; and a series negative feedback circuit having a capacitor connected between the source of the field effect transistor and a ground power source. Contains a gain flattening circuit.