JPH0440120A - Synchronization switching device for radio terminal station in synchronous network - Google Patents

Abstract

PURPOSE:To improve a characteristic while reducing the cost of a line switching device for a radio line requiring synchronous switching by enabling synchronous switching from an active line, which degrades a frame-synchronized multiplex signal, to an auxiliary line by an interface uniformed in all the world. CONSTITUTION:When the receiving terminal signal of an active line TP is degraded, a selector 201 of a switcher 20 in the switching circuit selects a frame pulse FSP outputted by a VC level termination part 10 on the auxiliary side, data DSP and clock CKSP at the level L of an output clock generated by a clock changer 30 and transmits them to a pointer processing part 40. The pointer addition part 40 writes the data DSP selected by the selector 201 of the switcher 20 and outputted from the VC level termination part 10 on the auxiliary side by the clock CKSP, reads it out by a reference clock DCS in a synchronous network and forms a data DSP' adding the required pointer value calculated by this reference clock DCS to the read data DSP.

Description

[Detailed Description of the Invention] [Summary] A protection line sp that inputs a synchronous multiplexed signal STM-n of a required number of frames in a predetermined format with frame synchronization from the world unified interface NNI via a transmission line and transmits it in parallel. and each receiving end signal of the working line TP, each row contains the overhead SOH at the beginning and the 9 bytes of the pointer PTH,
A basic frame S with a predetermined speed of 155.52 Mb/s consisting of 261 bytes of real information, 270 bytes in series, and 9 rows in parallel.
Regarding the synchronous switching device in a synchronous network that synchronizes with TM-1 and then performs bit synchronization for mutual switching, the hardware configuration of the switching circuit that performs synchronous switching from the working line to the protection line at the radio terminal station of the NNI synchronous network is as follows. The aim is to realize a line switching device that is simple and has a small delay in sending out signals at the receiving end of the switched protection line.
/s) Box VC-32's overhead S at the beginning of each of the three boxes
A protection and working VC level termination section that processes the OH and pointer PTR and synchronizes the frequencies of the protection line and working line boxes VC-32, and the protection and working VC level termination parts are connected to the protection line and working line boxes. Output spare and active frame pulses F Sr, F T when frequency synchronization of vC32 is achieved
P and data D Sr, D TP and clock CK Sr
, CK tr and a switch that selects the standby and the working, and a frame pulse and a clock that the switch selects by switching between the standby and the working, and the overhead SOH.
A switching circuit consisting of a clock switcher that generates the switching timing between H level and L level at the center of the time slot, and a required pointer PTR are added to the data DSPID TP of the output of the VC level termination section selected by the cough switching circuit. Equipped with a pointer addition section that also performs stuff processing, when the receiving end signal of the working line deteriorates, the switching circuit outputs a spare frame pulse F after synchronizing the frequency of the VC level with the protection side C level termination section. , P and data D8. and clock CK, , and the pointer addition section adds the required pointer PTR and also performs stuffing processing to create a basic frame ST? in a predetermined format. 1I-1 and is further stacked on the synchronous multiplexed signal STM-nSP of the required frame n and output.

[Industrial application field]

The present invention relates to a line switching device for switching to a protection line when the working line deteriorates in a receiving end station of a radio line, which is equipped with a protection line in addition to the working line in order to relieve failures due to fading or the like in a wireless transmission path.

In particular, frame synchronization is performed between the receiving end signal of the working line and the receiving end signal of the protection line from the new world-uniform network node interface NNI, and bit synchronization is also performed to prevent bit errors during switching and switchback. The present invention relates to a synchronous switching device for a wireless terminal station in a new synchronous network that switches to a receiving end signal of a line.

Worldwide unified network node interface NNI
is 1.5Mb/s in Japan and the United States x 4=, 6.
3Mb/s upper series and European 2Mb/s x 4
= Unify the asynchronous data (staff system) of the upper series of 8.4 Mb/s.

n x 155 Mb/s frame-synchronized multiplexed signal STM-n(S)+nchro in a predetermined format
nous TransportModule-Level
The line switching device of the receiving end station of the digital wireless line incorporated in the above-mentioned new synchronous network, which is a synchronous interface referred to as 1 n), is configured to transmit n-frame synchronously multiplexed data of STM-n from the above-mentioned synchronous interface NNI. On the other hand, line switching from the degraded working line TP to the protection line sp must be performed bit by bit, but it is desired that the circuit for this line switching has as simple a configuration as possible.

[Conventional technology]

As shown in FIG. 4, the conventional synchronous switching device in the new synchronous network described above transfers each receiving end signal of the working line TP and protection line SP input from the unified interface NNI via the wireless transmission path to each working and protection frame. Synchronous circuit FSYNCyr,
At FSYNC3F, frame synchronization of the STM-n signal of the working line and the STM-n signal of the protection line is performed for each basic frame STM-1, and then the serial/parallel converter S/P
tp, S/P Sr converts the input serial signal into a parallel signal, and then the delay device φ77. φ8. After absorbing the delay time difference between the working line and the protection line that varies due to fading, etc., the signal is input to the synchronization switching section of the station equipment, bit synchronization is achieved, and switching is performed. The synchronous switching unit transfers nx155 Mb/s of the n-frame multiplexed signal STM-n to a buffer memory IA of a dedicated LSI that stores 155 Mb/s for one frame, that is, n frames for each STM-1, and a synchronous network internal The working line T is equipped with a phase-locked loop PLL 2A consisting of a voltage controlled oscillator VCXO, etc. that generates a system clock CLK synchronized with the reference clock DC5 of
When the quality of the PO receiving end signal deteriorates, the working line TP is
After writing the similar protection line spO receiving end signal transmitted in parallel to the buffer memory 1^ and reading it out using the system clock CLK to achieve bit-by-bit synchronization, the receiving end signal of the deteriorated working line TP is The configuration is such that the signal is switched to the receiving end signal of the protection line SP at the basic frame STM-1 level and a multiplexed signal STM-nsp of the required frame is output.

[Problem to be solved by the invention]

As mentioned above, the conventional synchronous switching device uses a large-capacity buffer for writing and reading all the data of n frames in order to synchronize the frames of the working line TP and protection line SPO receiving end signals and then achieve mutual bit synchronization. Memory IA must be used, and the hardware configuration of the synchronization switching section of the terminal equipment at the receiving end of the line becomes large-scale.In addition, the reception of the protection line SP that is switched and sent out is required for writing and reading from and to the buffer memory IA. There was a problem in that the delay in transmitting the end signal became large. The problem of the present invention is to provide a switching circuit that performs synchronous switching from a working line with degraded reception quality to a protection line at a radio terminal station of the A network that transmits an n-frame synchronous multiplexed signal STM-n from a unified interface NNI. The object of the present invention is to provide a line switching device with a simple hardware configuration and with a small delay in sending out a receiving end signal of a switched protection line.

[Means for Solving the Problem] This problem is to solve the problem by transmitting an n-frame synchronous multiplexed signal n x 155 Mb/s STM-
n is the basic one frame STM-1 in bytes (
The basic frame STM-1 divides the total data of 155.52 Mb into 9 equal parts, as shown in the format shown in FIG.

It has a two-dimensional structure with 9 rows of 270 bytes each stacked in parallel,
The 270 bytes of each row consists of a section overhead SOH used for overall frame synchronization, 9 bytes of a management pointer PTR used for indicating the start position of subsequent real information and frequency synchronization, and 261 bytes of real information in series. . The 261 bytes of actual information are contained within the entire frame.
51.84Mb with 87 bytes each called VC-32
/s box (VC:Virtual Container)
) are multiplexed, and further inside the VC-32,
Focusing on the fact that 28 boxes of 1.7 Mb/s each with 3 bytes called VC-11 are multiplexed with one path overhead POH of the same 3 bytes, the basic configuration of the present invention is shown in Fig. 1. As shown in the principle diagram, a predetermined n-frame multiplexed signal STM-n at each receiving end of the protection line sp and the working line TP
After performing coding processing to eliminate the mutual fixed delay time difference and establish frame synchronization, the basic frame STM-1
Of the 261 bytes of actual information, each 87 bytes (51, 84
The protection and working VC processes the overhead SOH and pointer PTR at the beginning of each of the three VC-32 boxes (Mb/s) and synchronizes the frequencies of the protection line and working line boxes (VC-32). The level termination section 10.11 and the protection and working VC level termination section are connected to the protection line and working line box (VC
-32) Output spare and current frame pulses F Sr, F TP and data 03 when each frequency synchronization is achieved
P+ D TP and clock CK'SP, CKrp
and a switch 20 that selects the input for which the backup and current inputs have been exchanged.
and a switching circuit comprising a clock switching circuit 30, which switches between the standby and the working clock and sets the switching circuit to an H level at the center of the time slot of the overherer FSOH using the selected frame pulse and clock, and generates a level switching timing; Output data D of the VC level termination section 10.11 selected by the switching circuit! P', D Required pointer P to TP
It is equipped with a voice adding section 40 that adds TR and also performs stuff processing, and when the working line TPO receiving end signal deteriorates, the switching circuit synchronizes the frequency of the VC level with the VC level termination section 10 on the protection side and outputs it. The pointer addition unit 40 selects the spare frame pulse FSF, data DSF, and clock CKSF on the spare side, and adds a required pointer PTR and performs stuffing processing to create a basic frame S in a predetermined format.
TM-1 and a synchronous multiplex signal STM of the required frame
This problem is solved by the present invention, which is configured to output the problem by accumulating it in -n.

[Effect]

The VC level termination section 10 on the protection side and the VC level termination section 11 on the working side eliminate the fixed delay time difference between the predetermined n-frame multiplexed signals STM-n at each receiving end of the protection line sp and the working line TPO, and frame them. The signals after establishing synchronization are input, and the actual information 261 of the basic frame STM-1 is input.
By processing the overhead SOH and pointer PTH at the beginning of the three boxes of box VC-32, each 87 bytes (51.84 Mb/s) in the byte, the protection line and working line boxes VC-32 are processed.
By synchronizing the respective frequencies of D3.32, the preliminary and current frame pulses FSR, FTP and data D3. .

DTP and clocks CKsp and CKTP are input to the switch 20 of the switching circuit.

The switch 20 of the switching circuit has a VC level termination section 10.11.
Reserve and working frame pulses from 'SP+ FTP
and data D SP+ D TP and clock CKSP, C
Ktp, and the frame pulse F that replaced the spare and working
It consists of two types of selectors 201 and 20□ that input TP+F 3F, data D TP+D SF, and clocks CKtr and CKSP and select one output from two manual inputs.

The clock transfer device 30 of the switching circuit is connected to the selector 20 . is the frame pulse F that replaced the above-mentioned spare and working
TP, FSF, data DTP, DIF, and clocks CRTP, CKSP are inputted and the selected output allows the VC level termination section 10.11 to synchronize the respective frequencies of the protection line and working line boxes VC-32. The switching timing between the H level and the L level is generated at the center of the time slot of the overhead SOH when the switch is taken, and the selector 20. ．． 20! as a selected clock signal. Then, the selector 201 of the switch 20 of the switching circuit selects the frame pulse F TP, data D TP, and clock CKrp of the output of the VC level termination section 11 on the active side at the H level of the selected clock signal output from the clock transfer circuit 30. is selected, and at L level, the frame pulse psr and data Ds of the VCC level terminal part L trace output on the standby side are selected.
Select r and clock CK3F.

Therefore, when the working line TPO receiving end signal deteriorates, the selector 20 of the switch 20 of the switching circuit. However, the frame pulse FMW, data[)sP, and clock CK3F outputted from the VCC level terminal part l on the spare side are set to the level of the output clock generated by the clock transferer 30, and the VCC level on the spare side is changed to the VCC level on the spare side.
The frame pulse F3F, data DIF, and clock CKsp output from the C level termination section are selected and sent to the pointer processing section 40.

The pointer addition unit 40 is a selector 20 of the above-mentioned switch 20.
, writes the output data 01F of the spare side VC level termination unit 10 selected by the clock CKsp, reads it using the reference clock DCS in the synchronous network, and reads the read data D.
Data D! is obtained by adding a required pointer value calculated using the reference clock DC8 to SF! F', and performs stuff processing if necessary, and also absorbs fluctuations due to differences in the time ratio between level H and level L of the selected clock signal in the switch 20, the so-called duty ratio, from the normal value of 50%. as a basic frame STM-1 in a predetermined format,
Furthermore, it is multiplied by 1 in byte units, stacked into a synchronous multiplexed signal STM-n SF of the required number of frames n, and output.

Therefore, in the synchronous switching device for wireless transmission paths in a synchronous network according to the present invention, the switching circuit that performs synchronous switching from a working line with degraded reception quality to a protection line has a simple configuration of a switching device 20 and a clock switching device 30, Moreover, the switching is performed at the center of the time slot of the overhead SOH when the frequency synchronization of the three boxes VC-32 is established and terminated at the VC level termination section 10.11.

Receiving end signal STM-n SF of switched spare circuit gsp
The delay in sending out is reduced and the problem is solved.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a synchronous switching device for wireless transmission paths in a new synchronous network according to an embodiment of the present invention. Second
In the figure, the switch 20 of the switching circuit has a frame pulse F! P, F 1P selector 5EL21 +2h and data (1!P, D TP selector SEL 22+
, 22g and clock CK3P, selector S for CKTP
Consists of EL 23+, 23z, SEL 21+
and SEL 22+ and SEL 23+ are selector 2
0. consists of SEL 21□, SEL 22z and 5E
L23□ constitutes the selector 2 (h. Also, the pointer processing unit 40 is composed of a pointer calculation circuit 41, an elastic memory 42, and an SOH multiplex circuit 43.Other symbols and numbers are the same as those already explained. These circuits have the same symbols and numbers as in FIGS. 1 and 4.

The clock transfer device 30 of the switching circuit is a two-person frame pulse store F+ in which the SEL 21□ of the selector 20□ of the switching device 20 exchanges and inputs the outputs of the backup and working VC level termination sections 10.11. F SF and data D7P+
At the center of the time slot of the overhead SOB when the VC level termination section 10.11 synchronizes the respective frequencies of the protection line and the working line box VC-32 by selecting the output of 03F and the clocks CKTP and CK3F, Generates the switching timing between H level and L level, and all selectors 201.20□ of the switch 20 of the switching circuit are SEL, 21
+ to 238 as a 1 selection clock signal. and.

All 5EL21I to 23□ of the switch 20 are set to 2 at the H level of the selected clock signal output from the clock transfer device 30.
Input terminal B of the input terminal is selected, and at L level, select the input terminal and output.

Therefore, when the working line TPO receiving end signal deteriorates, the selector SEL of the switch 20 of the switching circuit 22. , SEL 23
．． However, depending on the level of the selected clock signal generated by the clock transfer unit 30, data 03F and clock CK output from the VC level termination unit 10 on the standby side are selected and input to the elastic memory 42 of the pointer processing unit 40. 5EL
21 selects the frame pulse p sp and inputs it to the SOH multiplex circuit 43 .

The elastic memory 42 of the pointer adding unit 40 stores the V of the spare side selected by the selector SEL 22+ of the switch 20.
The data D Sp output from the C-level termination unit 10 is written using the clock CK3F selected by the selector SEL 23+, read from the pointer value calculated by the pointer calculation circuit 41 using the reference clock DC3 in the synchronous network, and the pointer value is added. Data D8. ', SOH multiplex circuit 4
Enter to 3.

The SOH multiplex circuit 43 adds frame pulses F8 . and multiplex it. Then, if necessary, staff processing will be carried out,
Also, the level H and level L of the selected clock signal at SEL 23+ of the switch 20 (7) Time ratio dut
A basic frame STM-1 of a predetermined format is obtained by absorbing the variation from the standard 50% value of the y ratio, and is further multiplied by 0 in byte units to obtain a synchronous multiplexed signal STM-n of the required number of frames n.
It is stacked in sr and output.

Therefore, the wireless transmission path synchronous switching device in the synchronous network according to the embodiment of the present invention shown in FIG.
A switching circuit that performs synchronous switching from P to protection line SP is composed of a simple switching device 20 and a clock switching device 30. -32 frequency synchronization is established and terminated at the center of the overhead SOH time slot, so the receiving end signal STM-n of the switched reserved AM line sp is
3. The delay in sending is reduced and there is no problem.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to synchronously switch from a deteriorated working line to a protection line of a multiplexed signal frame-synchronized with a world-uniform interface NNI using a switching circuit with a simple configuration. It is possible to reduce the cost and improve the characteristics of a line switching device for a wireless line that requires synchronous switching in the future.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram showing the basic configuration of a synchronous switching device of a wireless terminal station in a synchronous network of the present invention. FIG. 2 is a block diagram showing the configuration of a synchronous switching device of a wireless terminal station in a synchronous network of an embodiment of the present invention. 3 shows the basic frame STM of the NNI signal for detailed explanation of the present invention.
-1 format, FIG. 4 is a block diagram of a conventional synchronous switching device in a synchronous network. In the figure, 10.11 is a VC level termination section, 20 is a switch, 21. -23□ is a selector SEL, 30 is a clock transfer device, and 40 is a pointer adding section.

Claims (1)

[Claims] A protection line (STM-n) for inputting a synchronous multiplexed signal (STM-n) of a required number of frames (n) of a predetermined format, frame-synchronized by a unified interface (NNI), through a transmission line and transmitting it in parallel. Each row contains the overhead SOH and pointer PTR (SP) and the receiving end signal of the working line (TP).
7) Serial (a + b) bytes (270 bytes) of a byte (9 bytes) and subsequent b bytes (261 bytes) of real information, parallel a rows (9 rows) at a specified speed (155.52 Mb)
In a synchronous switching device in a synchronous network that performs frame synchronization of a basic frame (STM-1) with /s), further bit synchronization, and mutual switching, the real information b byte of the basic frame (STM-1) is Overhead SOH at the beginning of c boxes (VC-32) of 1/c bytes each (87 bytes, 51.84 Mb/s)
and pointer PTR to the protection line and working line boxes (V
The protection and working VC level termination parts (10, 11) synchronize and output the respective frequencies of the protection line and the working line (VC-32), and the protection and working VC level termination parts connect the protection line and the working line box (VC-32).
32), the preliminary and current output frame pulses (F_S_P, F_T_P) and data (D_
S_P, D_T_P) and clocks (CK_S_P, CK
_T_P) and a switch (20) that selects the input for which the standby and working are switched, and the frame pulse and clock that select the input for which the standby and the working are switched of the output of the switch, and the time of the overhead SOH. A switching circuit consisting of a clock switcher (30) that generates switching timing between H level and L level at the center of the slot, and output data (D
It is equipped with a pointer addition section (40) that adds a required pointer PTR to the VC level termination section (_S_P, D_T_P) and also performs stuffing processing. ) to synchronize the frequency of the VC level and output the spare frame pulse (F_
S_P), data (D_S_P) and clock (CK_S
_P) is selected, and the pointer addition unit (40) adds a required pointer PTR and performs stuffing processing to make it a basic frame (STM-1) in a predetermined format, and further to a synchronous multiplex signal (STM-n_S_P) of the desired frame. A synchronous switching device for a wireless terminal station in a synchronous network characterized by stacking and outputting.