JPH0440544A - Processing system for input and output instructions for test - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 5 to 7) Problems to be solved by the invention Means for solving the problems (Figure 1) Working examples (Figures 2 to 4) Effects of the invention [Summary] Regarding the test input/output command processing method, when testing a channel adapter, a response to a test OUT command is returned immediately, and a response to a test IN command is returned. The purpose is to control the response so that it can be varied depending on the state of the channel adapter.
a central control unit that controls the adapter according to input/output instructions;
It has a monitoring means for instructing the channel adapter to start or end a test, and when the monitoring means issues a test start instruction, the channel adapter loops back the channel interface, and the central control unit executes an interlon by a test input/output command. In a device for simulating a data type channel interface, when an output command for testing is transmitted from the central control unit, the processor saves the data in the tag-in holding means in the holding means, and also transmits the output command to the tag-out holding means. When a test input command is transmitted, a timer is started, and when the timeout expires, the data in the saved storage means and the tag-in storage means are compared by the 11 sensors, and if they do not match, the data for the input command is The configuration is configured to return a response, restart the timer when a match occurs, and return a response to the input command even when the number of activations of the timer reaches a predetermined value.

[Industrial application field]

The present invention relates to a test human output command processing method.

Due to advances in microprocessors in recent years, devices that were previously made using hardware are now being made using firmware. Since such devices involve asynchronous processing, a method of processing using interrupts is often used. If there is an interrupt process, the timing of interrupt generation changes depending on the firmware change, and therefore a large number of man-hours are required to verify the operation and test the device. Therefore, it has become essential to automate testing.

The present invention relates to automatic testing of such devices.

[Conventional technology]

For example, the channel adapter 4 of the communication control processing device 40
As shown in FIG. 5, which describes case 1, the communication control processing device 40 connects a channel 52 and a channel adapter 4 to a post 1-processor 5 provided in a host 50.
connected via.

Further, the communication control processing device No. 40 is provided with a plurality of line units 44-0.44-1-/I/I-n,
One to a plurality of terminal devices are connected to each of the lines connected to these lines, and data processing for the host computer 51 is performed. The line scanner 44 sequentially scans the states of the line units 44-0 to 44-n to control communication with the host processor 51.

The communication control processing device 40 is provided with a central control section 42 and a main storage section 43.
Reads the instructions stored in and executes them. Further, the channel adapter 41 controls the interlonter type channel interface according to instructions from the central control unit 42.

Note that 48 is a system hub to which the main storage section 43, central control section 42, channel adapter 41, etc. are connected. And the channel adapter 41 has a microprocessor 45.
, tag-in register 46, tag-in register 4
7th grade is provided. Data transmitted from the channel interface to the channel adapter 41 is once sent to a tag register 464, and data sent from the channel adapter 41 to the channel interface is once sent to a tag register 47. .

By the way, in addition to instructions for controlling the channel adapter 41, the main storage unit 43 also contains instructions for controlling the channel interface.
Test commands and the like are stored. and monitoring section 4
9 monitors the central control unit 42 and channel adapter 41, and instructs the start and end of the loopback test.

When testing the channel adapter 4J, the monitoring unit 49
instructs the channel adapter 41 and central control unit 42 to start the test. This controls the channel adapter 41 so that it does not send data from the channel 52 to the channel 52.

The central control unit 42 issues a test out command to the channel adapter 41. Channel adapter 41
When the microprocessor 45 receives the test out instruction, it writes the data issued by the test out instruction to the tagout register 46.

Next, the central control unit 42 issues a test in command to the channel adapter 41.

When the microprocessor 45 of the channel adapter 41 receives the test-in command, it responds with the data held in the tag-in register 47.

It is checked whether the data read by this eggplant 1~in instruction matches the expected value or not. If they match, it is considered normal and the next test i- is performed, and if they do not match, error handling is performed. In this way, the channel interface in the channel adapter 41 is tested. FIG. 6 shows this test sequence.

By the way, the channel adapter 41 processes the out command and in command as follows.

The microprocessor 45 has a plurality of program execution levels, and at the first level, instructions issued from the central control unit 42 are processed.

At the lower level, a change in the tagout register 46 is detected and the tagin according to the channel interface is sent to the tagin register 47.

As shown in FIG. 7, the out instruction and in instruction are each processed at a higher level.

When the out command is issued by the central control unit 42 and received by the microprocessor 45, the process of writing the issued data into the tag out register 46 is performed at the same time.

When the processing of the out instruction is completed, a change in the contents of the tag-out register 4G is detected at a lower level, and processing is performed to transfer the tag-in according to the channel interface to the tag-in register 47. Therefore, as shown in FIG. 7, at time 1. When an out command is issued from the central control unit 42 at time o, the microprocessor 45 executes upper-level processing, starts setting data in the tagara I~ register 46, and at time 1+ returns to normal lower-level processing. This tagout register 4 is processed by level processing.
The operation is started to set the tag-in for the data set to 6 in the tag-in register 47.

By the way, if the input of data to the tag-in register 47 is not completed or if an IN instruction is issued from the central control unit 42 while it is being executed, for example, if this IN instruction is issued at time t2 indicated by a dotted line, the microblock is Se・
The sensor 45 shifts to processing at the -L level and outputs the data in the tag-in register 47 to the central control unit 42. However, at this time, the tagara l~・register 4
Since the tag-in for the tag-out set to 6 has not been written to the tag-in register 47, the data read from the tag-in register 47 does not match the 1-1 wait value. Therefore, the central control unit 42 mistakenly recognizes that the channel adapter 41 is in error.

When an error is recognized in this way, the central control unit 4
From step 2, an IN command is issued to dump the current state. However, if the channel adapter 41 suspends the response to this IN instruction until the data set in the gain register 47 is completed in the evening, and the response times out for some reason, the IN instruction for dumping will also time out. This has the disadvantage that it is not possible to later analyze in what condition the IN instruction times out.

Therefore, as a possible solution to this drawback, there are two methods: (1) suspending the response of the out command for testing until time t4, which is 3 years after the time when the firmware completes data entry to the tag-in register 47; The test program stored in the main storage unit 43 was created so that the central control unit 42 would issue an IN command at time t5, which is the time when data is set in the tag-in register 47.

[Problem to be solved by the invention]

However, as in (2) above, when suspending the response to the out command for testing, data is set in the tagout register 46 to change the state, and then the tagin register 47 is updated with the tagin data for that tagout. There was a problem that detailed tests could not be performed because other input/output commands could not be issued. The part of the firmware that controls the tag-in register requires processing for testing, leading to the complexity and size of the firmware.

In addition, as in (■) above, if a test program is created with an allowance for the time it will take to set data in the tag-in register 47 and change its state, the estimated time will not be sufficient due to firmware changes. Problems such as these may occur, requiring changes to the test program.

Therefore, an object of the present invention is to provide a method for processing input/output instructions for testing which improves the above-mentioned problems.

[Means to solve the problem]

To achieve the above object, as shown in FIG. 1, the channel adapter is equipped with a microprocessor I, a controller 1-roll strain 2, and a timer 3, and the microprocessor 1 is equipped with a comparator 1-0. A counter 1-1 is provided.

Of course, the channel adapter has tagout register 4.
and a tag-in register 5 are provided, and a gate 1-6 is provided on the input side of the tag-out register 4, to which data from the channel interface or data from the microprocessor 1 is selectively sent.

In addition, a save area 20 for saving the data of the tag-in register 5 is provided in the control units 1 to 2.

[Operation] When an out command is transmitted from the central controller (not shown in FIG. 1) to the microprocessor 1 to test the channel adapter, the microprocessor 1 first reads the contents of the tag-in register 5. , save this in control strain 2's sub-area 2-0. Then, the data transmitted from the central control unit at the time of the out command is sent to the tagout register 4 by turning on the get 6.
~do. When the processing of the out instruction is completed, the process of writing the tag-in for the data sent to the tag-out register 4 into the tag-in register 5 is started. Then, when the IN command is transmitted to the microprocessor 1 from the central control section, the microprocessor 1 starts the timer 3. When the interrupt signal is transmitted to the microprocessor 1 after the timer 3 has elapsed for a certain period of time, the microprocessor 1 saves the data saved in the save area 2-0 and the data set in the tag-in register 5 at that time. are compared by comparison unit 1-0.

At this time, if the data set in the tag-out register 4 has been sent to the tag-in register 5, the comparator 1-0 detects a mismatch, and if the data has not been set, it detects a match.

If a match is detected, microprocessor 1 increments counter 1-1 by 1 and restarts timer 3. Then, when the interrupt signal is transmitted again from the timer 3 after a certain period of time, the same comparison is performed.

At this time, if the tag-in data for the tag-out has already been sent to the tag-in register 5, the comparator 1-0 outputs a mismatch signal. As a result, the microprocessor 1 outputs a response signal in response to the IN command from the central control section.

In response to the response signal of this IN instruction, the central control unit reads the data in the tag-in register 5, and if this is the expected value, the channel adapter is determined to be normal, and if it is not the expected value, it is determined to be abnormal.

In this way, other input/output commands can be issued from the central control unit to the sections that were previously suppressed.

〔Example〕

An embodiment of the present invention will be described based on FIGS. 2 to 4.

FIG. 2 shows a channel adapter configured as an embodiment of the present invention.
FIG. 3(A) is a timing chart explanatory diagram of the present invention;
FIG. 4B is an explanatory diagram of the control memory of the present invention, and FIG. 4 is a flowchart 1- for explaining the operation of the present invention.

FIG. 2 shows a channel adapter according to the present invention, and the system configuration includes a channel adapter 41 shown in FIG.
This corresponds to

In FIG. 2, the same parts as in FIG. 1 are indicated by the same symbols.

The timer 3 includes a counter 3-0, a zero detector 3-1, an AND gate 3-2, 3-3, an OR gate 3-4, and a subtracter 3-
5. Fill in-holes 3-6 (rtii) and 10
is a flip 70-tube (hereinafter referred to as FF) for holding an interrupt signal, 11 is an OR gate, 1-112 are AND gates, and 13 is an inverter.

In addition, in Control S) Rain 2, Figure 3 (■3
), the channel adapter firmware 2-
1, a save area 2-0 for saving the data of the tag-in register 5, an interrupt count holding area 22 for specifying the number of interrupts from the timer 3, etc. are prepared, and this interrupt count holding area 2-2 The upper limit of the number of interrupts from timer 3 is written in advance.

Next, the operation of the present invention will be explained.

(2) When testing the operation of the channel adapter, a monitoring section (not shown) (see FIG. 5) instructs the channel adapter and the central control section to start the test. This will test the channel adapter.
In order to do this, the central control unit issues a test out command to the channel adapter.

In addition, the channel adapter is gated so that test data is not output to the channel.

(2) As shown in flowchart 1 of FIG. 4(A), when this out command is transmitted, an interrupt for this out command is generated in the firmware of the channel adapter. This causes the microprocessor 1 to then read the tag-in register 5 and save it in the save ZU Mi 2-0 of the control strain 2. Next, the data of the out command transmitted from the central control unit is set in the tag register 1-register 4. Then, a tag-out response is output to the central control unit. This interrupt processing is performed by the third
As shown in Figure (A), the processing is performed at the - level of the microprocessor 1.

■ After the microprocessor 1 has sent the data in the tagout register 4 through processing at the upper level, it sets the tagin in the tagin register 5 for the data 1 to 1 sent to the tagout register 4. processing is performed at a lower level.

(2) The central control unit issues a test IN command at time 1'o, not shown in FIG. 3(A), in order to confirm the OUT command. This causes an interrupt to be generated in the channel adapter's firmware to process the next in command. As a result of the interrupt processing, the timer is activated as shown in flowchart 1 of FIG. 41(B).

Thus, the microprocessor 1 outputs "l" to the game 1-3-2 shown in FIG. 2 in order to start and control the timer 3. At this time, since a fixed value is input to Antogame) 3-2, this fixed value is input to Andogame 3-2.
, or-1-3-4 to the counter 3-0. The counter 3-0 is then set to the respective fixed value. This starts timer 3, and the 1' l 4
becomes 10. Therefore, inverter 3-6 is "1"
is output, and the ant gate 3-3 is now turned on. The output of the counter 30 is subtracted by -1 by a subtracter 3-5, and the value subtracted by -1 is input to the AND gate 3-3.
Sent to counter 3-0 via OR gate 3-4]
Therefore, the counter 3-0 eventually subtracts by 1 in accordance with the operation counter. Then, when the output of the counter 30 becomes all zero, that is, zero, this is detected by the zero detection section 3-
1 is detected, "1" is output from the zero detection unit 3-1, OR gate ]1 also outputs [1], F F ],
O is thereby set and outputs an interrupt signal "1".

■ As a result, as shown in the flow chart shown in FIG. 4(C), the microprocessor 1 sends the reset signal "1" to the inverter 13 in order to reset this interrupt signal.
Output to. As a result, the inverter 13 outputs "OJ", the AND gate 12 and the OR gate 11 output "OJ", and the FF 10 is reset.

By the way, in response to the interrupt signal from F F ] 0, the microprocessor 1 reads the first data of the tag-in register 5 held in the save area 20, and at this time, the data set in the tag-in register 5 is read out. Then, compare these data with the comparison section 1-0.
Compare with. If they match, it indicates that the tag-in register 5 has not been rewritten, so the counter 1-1, which is initially set to zero, is incremented. Then, the comparator 1-0 compares whether the value of this counter], -1 matches the number of interrupts set in the interrupt number holding area 22. If there is a mismatch, that is, if the predetermined number of interrupts has not been reached, the microprocessor 1 outputs the timer activation signal again and performs the same control as described above (setting the fixed value to 7 to the counter 3-0). conduct.

■ By the way, in the above (■), if the data held in the save area 20 and the data in the tag-in register 5 do not match, it means that the tag-in register 5 has been rewritten with the tag-in data corresponding to the data in the tag-out register 4. Therefore, the microprocessor 1 outputs a response to the IN command, clears the counter 1-1, and sets the number of interrupts to O.

(2) In addition, when the timer is started again in (2) and the same control is repeated until the number of times recorded in the interrupt count holding area 2-2 is reached, the microprocessor 1 outputs a response to the IN instruction, Clear the counter 1-1 and set the number of interrupts to 0.

In response to this in command, the central control unit performs tag-in.
The operation of the channel adapter is diagnosed by reading the data in the register 5 and comparing it to see if it matches a predetermined value. In the above case (2), it is diagnosed as a normal state, and in the above case (2), since it does not match the predetermined value, it is determined that the state is in an abnormal state, and processing corresponding to each case is performed.

FIG. 3(A) is a timing chart showing the state of decline in the above-mentioned (2). At time TO, an IN command is transmitted from the central control unit, the timer is started, and at time TI, when the timer outputs an interrupt signal, the data in Fuguara 1-Register 4 has not been written to Tag-in register 5. Therefore, timer 3 is restarted. Then, at time T2, the tag-in for the data in the tag-out register 4 is set in the tag-in register 5, so that when the interrupt signal from the timer is output at time T3, a response to the IN instruction is output.

In the above explanation, an example was explained in which the data of the tag-in register 5 was set in the save key area 2-0 of the control strain 2, but the present invention is of course not limited to this, and other holding means, For example, it may be saved using registers. Also, counter 3 for timer
We have explained an example of setting 11 subtraction data as -0, but of course an addition counter is used to set a constant value to 1
- It may be configured to output an interrupt signal when an event occurs.

〔Effect of the invention〕

According to the present invention, other input/output commands can be issued to the channel adapter during the period in which the response to the OUT command is suppressed, so that detailed tests 1 to 1 can be performed. Further, processing specific to testing in firmware can be limited to interrupt processing, making firmware development and maintenance easier. Furthermore, when creating a test program, it is not necessary to take into account the time that the data in the tag-in register changes, so the test program can be created easily.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the present invention, Fig. 3 (A) is an explanatory diagram of the timing chart 1 of the present invention, and Fig. 3 (B) is FIG. 4 is a flowchart 1-1 for explaining the operation of the present invention. FIG. 5 is an explanatory diagram of the configuration of the communication control processing device and the connection state with the boss L. FIG. 6 is a conventional test state. Explanatory Flow Chart FIG. 7 is a time chart for explaining problems in the conventional test state. Microprocessor control strain timer tag register 1-register tag-in register

Claims (1)

[Claims] A channel adapter controlled by firmware having a plurality of program running levels, a central control unit that controls the channel adapter using input/output commands, and a central control unit that instructs the channel adapter to start or end a test. When the monitoring means issues a test start instruction, the channel adapter loops back the channel interface, and the central control unit simulates an interlock type channel interface by input/output commands for testing. A processor (1) that performs processing based on test output commands and input commands issued from the control unit, a tag-out holding means (4), a tag-in holding means (5), and a timer (3). , has a holding means (2-0) for saving the data of the tag-in holding means (5), and when a test output command is transmitted from the central control unit,
The processor (1) saves the data of the tag-in holding means (5) in the holding means (2-0), holds the contents of the output command in the tag-out holding means (4), and transmits the input command for testing. When the timer (3) is activated, the saved holding means (2) is started due to the timeout.
-0) and the tag-in holding means (5) are compared by the processor (1), and if they do not match, a response to the input command is returned, and if they match, the timer is restarted, and the number of times the timer is started is set to a specified value. An input/output command processing method for testing is characterized in that a response to an input command is returned even when the input command is reached.