JPH0440778A - Image signal recording and playback system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image signal recording and reproducing system that records an image signal on a recording medium and reproduces the image signal recorded on the recording medium.

[Conventional technology]

2. Description of the Related Art Video tape recorders and electronic still video systems are conventional image signal recording and reproducing systems that record image signals on a recording medium and reproduce the image signals recorded on the recording medium.

In the above-mentioned system, in order to correct the time axis fluctuation that occurs when reproducing an image signal from a recording medium, a clock signal having the same time axis fluctuation as the image signal reproduced from the recording medium is formed, and the clock signal is After synchronizing and digitizing the reproduced image signal, it is temporarily stored in a memory, etc., and when reading the image data from the memory, the image data is read out in synchronization with an accurate lock signal that does not cause time axis fluctuations. The so-called TBC (Time Base) corrects the time axis fluctuations that occur in the reproduced image signal during reproduction.
5e Correction) technology is used.

In addition, in the above-mentioned TBC technology, when forming a clock signal having the same time axis fluctuation as the reproduced image signal, in the case of a video tape recorder, a color burst signal added in advance to the image signal is used to generate the color burst signal. A clock signal that is phase-synchronized with the signal is used as a PLL (Phase L).
However, in the case of an electronic still video system, there is no signal with time axis information such as a color burst signal, so the rising or falling edge of the horizontal synchronizing signal added to the image signal is A clock signal that is phase-synchronized with is generated by a PLL circuit or a gated oscillator.

However, with the method using the horizontal synchronization signal described above, if the S/N ratio of the reproduced image signal is poor, it is not possible to accurately detect the rising or falling edge of the horizontal synchronization signal, and accurate correction of time axis fluctuations cannot be performed. It had the disadvantage of not being able to do anything.

Therefore, in an electronic still video system, when recording an image signal on a magnetic disk as a recording medium, the applicant has developed an FM modulated color signal frequency band C-F as shown in Figure 's3.
A pilot signal f with a frequency (for example, 2.5 to 3.5 MHz) between M and the FM modulated luminance signal frequency band Y-FM
p as a reference signal for TBC, it is frequency-multiplexed near the horizontal blanking period (H-BLK) and near the vertical blanking period (V-BLK) of the image signal, and then recorded, and during playback, it is frequency-multiplexed with the image signal. We devised a method of forming a clock signal having the same time axis fluctuation as the reproduced image signal using a PLL circuit or the like using a recorded pilot signal as a reference.

FIG. 4 is a diagram showing a schematic configuration of a reproducing device in a conventional image signal recording and reproducing system.

In order to simplify the explanation, the image signal is assumed to be a black-and-white image signal, and FIG. 4 shows a schematic configuration of a reproduction apparatus for a black-and-white image signal.

In FIG. 4, a reproduction signal reproduced by a magnetic head 3 from a magnetic disk 1 rotated by a motor 2 is amplified by a reproduction amplifier 4 and then supplied to a demodulation circuit 5 and a pilot signal separation circuit 8.

The demodulation circuit 5 demodulates the supplied reproduced signal into a baseband signal and supplies it to the synchronization separation circuit 6 and the TBC circuit 7.

Further, from the reproduction signal amplified by the reproduction amplifier 4, a pilot signal separation circuit 8 separates the pilot signal frequency-multiplexed with the image signal during recording, and further amplifies the pilot signal fp to an appropriate amplitude level. The signal is supplied to a phase comparator 9.

By the way, the other input terminal of the phase comparator 9 has a VCO (
Clock signal fS output from voltage controlled oscillator) 10
C is divided by a frequency divider 11 into a signal fp having approximately the same frequency as the pilot signal fp, and the phase comparator 9 outputs an Erani voltage Vp corresponding to the phase difference between the signals fp and fp' to the switch SL. bta and sample hold (S/H) circuit 12.

The switch SL either supplies the error voltage Vp output from the phase comparator 9 to the loop filter 13 via the sample-and-hold (S/H) circuit 12 (if the switch S1 is connected to the a terminal in the figure), or outputs it as is. Loop filter 13
(When switch S is connected to terminal b in the figure) controlled.

The switching control operation of the switch S1 will be described below.

The vertical blanking pulse generator 15 in FIG. 4 receives a PG pulse generated from a PG coil (not shown) every time the magnetic disk rotates once, and a composite synchronization signal separated from the reproduced image signal by the synchronization separation circuit 6. C-3YNC is supplied from the vertical blanking pulse generator 15, and the vertical blanking pulse signal V-BLK is at a high level during the period from the falling edge of the PG pulse to the end of the vertical synchronization signal.
is output to the switch Sl, and the switch S1 is connected to the b side in the figure during the period when the vertical blanking pulse signal V-BLK is at the high level, and is connected to the terminal a in the figure during the period when the vertical blanking pulse signal V-BLK is at the low level.
Connected to the terminal side.

Also, the composite synchronization signal C separated by the synchronization separation circuit 6
-5YNC is also supplied to the sample-and-hold pulse generator 14, and from the sample-and-hold pulse generator 14, a sample-and-hold pulse SHP is supplied to the S/H circuit 12 in synchronization with the supplied composite synchronization signal C-3YNC, The S/H circuit 12 receives the supplied sample and hold pulse S.
The error voltage Vp supplied via the switch S1 is sampled and held according to HP.

As described above, the pilot signal fp separated by the pilot signal separation circuit 10 of FIG. 4 is phase-compared with the signal fp' supplied from the frequency divider 11 in the phase comparator 9, and The error voltage Vp corresponding to the phase difference is supplied to the switch Sl, and the switch s
By controlling the l, s, /H circuits 12, a continuous error voltage Vp is supplied to the loop filter 13 while the vertical blanking pulse signal V-BLK is at a high level.
During the other periods, the error voltage Vp sampled and held every IH is supplied.

After the error voltage Vp is band-limited by the loop filter 13, it controls the frequency of the clock signal fsc (=Nfp, N is a positive integer) output from vcoto, and is output from the demodulation circuit 5 from VCOIO. A clock signal fsc having the same time axis fluctuation as that of the baseband image signal is generated and supplied to the TBC circuit 7.

With the above configuration, the phase comparator 9 and VCO in FIG.
lo, frequency divider 11, S/H circuit 12, loop filter 1
3. The frequency of the clock signal fSC formed by the PLL circuit constituted by the switch s1 is the frequency of the sideband wave of the pilot signal fp±nfH (n is a positive integer,
It is possible to prevent phase synchronization with fH (frequency of the horizontal synchronization signal), and it becomes possible to correct time axis fluctuations with high accuracy.

Then, in the TBC circuit 7, the supplied baseband image signal is digitized in synchronization with the clock signal fsc supplied from vcoto, and after being stored in a memory or the like,
Read from the memory in synchronization with an accurate lock signal,
By converting it again into an analog baseband image signal, the TBC circuit 7 outputs a baseband image signal from which time axis fluctuations have been removed.

[Problem that the invention is trying to solve]

However, in the above conventional example, the frequency of the clock signal fsc formed by the PLL circuit is different from the pilot signal f.
Although it is possible to prevent phase synchronization with the frequency fp±nfH of the pO sideband, it is necessary to provide a switch S1, which complicates the configuration, and the loop filter 13
There is a problem in that it is difficult to manually set the DC bias voltage, etc., and the configuration becomes even more complicated in order to perform stable correction of time axis fluctuations.

The present invention was made to solve such problems,
It is an object of the present invention to provide an image signal recording and reproducing system that can reliably and stably remove time axis fluctuations of an image signal that occur during reproduction with a simple configuration, and that can reproduce an image signal with accurate time axis. purpose.

[Means to solve the problem]

The image signal recording and reproducing system of the present invention is a system that records a single-frequency pilot signal together with an image signal on a recording medium, and reproduces the image signal recorded on the recording medium, the system comprising: at least a horizontal direction of the image signal; a recording means for adding a single frequency pilot signal during a vertical blanking period and recording it on a recording medium; and a sampling clock for generating a sampling clock signal for sampling an image signal separated from a signal reproduced from the recording medium. a phase generator for separating a pilot signal from a reproduced signal reproduced from the recording medium, comparing the phases of the separated pilot signal and the sampling clock signal, and outputting a phase error signal according to the result of the phase comparison; Comparing means; Clamping means for clamping the phase error signal output from the phase comparison means and supplying the clamped phase error signal to the sampling clock generation means; Clamped phase error output from the clamping means. sample and hold means for sampling and holding a signal and supplying the sampled and held phase error signal to the sampling clock generation means; a first pulse signal generation means for outputting a first pulse signal corresponding to the vertical blanking period; The first pulse signal output from the first pulse signal generating means is used to form a clamp pulse signal that controls the clamp operation in the clamp means and a sample hold pulse signal that controls the sample hold operation in the sample hold means. and a phase error signal clamped by the clamping means and sampled and held by the sample-holding means to control the phase of the sampling clock signal generated by the sampling clock generation means. The system is equipped with a control means for controlling.

[Effect]

According to the above configuration, with a simple configuration, it is possible to reliably and stably remove the time axis fluctuation of the image signal that occurs during reproduction, and it becomes possible to reproduce the image signal with accurate time axis.

〔Example〕

Hereinafter, the present invention will be explained using examples of the present invention.

FIG. 1 is a diagram showing a schematic configuration of a reproducing device in an image signal recording and reproducing system to which the present invention is applied, as an embodiment of the present invention.

In order to simplify the explanation, here, the image signal is assumed to be a monochrome image signal, similar to the conventional example reproducing apparatus shown in FIG. 4, and FIG. Indicated.

Further, in the reproducing apparatus shown in FIG. 1, the same components as those of the reproducing apparatus shown in FIG.

The operation of the embodiment shown in Figure 's1 will be explained below. Incidentally, FIG. 2 is a timing chart showing signal waveforms at each part in FIG.'s1.

In FIG. 1, a reproduction signal reproduced by a magnetic head 3 from a magnetic disk 1 rotated by a motor 2 is amplified by a reproduction amplifier 4 and then supplied to a demodulation circuit 5 and a pilot signal separation circuit 8.

Note that the reproducing apparatus of this embodiment uses the conventional reproducing apparatus shown in FIG. 4 and the PLL that forms the clock signal fsc.
Since the circuit configuration and its operation are different, the differences will be explained below.

The pilot signal fp (see FIG. 2(a)) frequency-multiplexed with the image signal during recording is separated in the signal separation circuit 8 to which the reproduced signal is supplied as described above.
After being further amplified to an appropriate level, it is supplied to the phase comparator 9.

By the way, the other input terminal of the phase comparator 9 has a VCO (
[Pressure controlled oscillator) The frequency output from 10 is 3.07
Clock signal f, of MHz=195fH. is the frequency divider 11
A band pass filter (BPF) which divides (for example, divides the frequency by 1/7) into a signal with a frequency almost equal to that of the pilot signal fp and passes only a signal with a frequency of 195 fH.
16, and the phase comparator 9 generates an error voltage VP according to the phase difference between the signals fp and fp'.
ri, a clamp circuit 17 composed of a constant voltage source E1
supplied to

The clamp circuit 17 generates an error voltage V when the transistor Tr is turned on by a pulse signal (d) (see FIG. 2(d)) output from an AND gate 24 (described later).
It clamps p to voltage E, and outputs it without clamping when it is turned off (see FIG. 2(h)). Note that the value of the capacitor Co is preset to a large value in order to maintain the DC level at the voltage El during the vertical blanking period.

By the way, the composite synchronization signal C-5YNC separated from the baseband image signal demodulated by the synchronization separation circuit 6 is supplied to the 1/2H killer circuit 22 and the vertical synchronization signal separation circuit 28. 22 removes the equalization pulse from the supplied composite synchronization signal C-5YNC and supplies it to the mono multivibrator (M-M) 23.25.
- A ramp pulse (b) is outputted from M23 as shown in FIG. 2(b), and is supplied to one input terminal of the AND gate 24.

Further, the vertical synchronization signal separation circuit 28 separates the vertical synchronization signal from the supplied composite synchronization signal C-3YNC, and further uses M-M29.30 to separate the vertical synchronization signal from the supplied composite synchronization signal C-3YNC. A pulse signal (C) that is at a low level only during the vertical blanking period as shown in FIG.

Therefore, a ramp pulse (d) is supplied from the AND gate 24 to the clamp circuit 17 as shown in FIG. , clamps the error voltage Vp (see FIG. 2(h)).

Then, the error voltage Vp clamped in the lamp circuit 17 as described above is supplied to the sample and hold circuit 18 constituted by the FETI and the capacitor C1, and is output from the collector of the transistor Tr2, which will be described later, as shown in FIG. 2(g). Sample hold pulse as shown in (
The sample is held according to g).

An AND gate 27 is connected to the base of the transistor 7r2.
A pulse signal (f) as shown in FIG. Using the signal C-5YNC, the M-M2S, 26 forms a pulse signal (e) as shown in FIG. Further, the other input terminal of the AND gate 27 is supplied with the pulse signal (C) output from the M-M2O as described above, and the AND
From the gate 27, a pulse signal Cf shown in FIG. 2(f) is output.
is supplied to the base of the transistor Tr, and the sample and hold pulse (g) is supplied from the collector of the transistor Trz to the sample and hold circuit 18 as described above,
During the period when the sample and hold pulse (g) is at a high level, FETI is turned ON, and the error voltage Vp (see FIG. 2(h)) output from the clamp circuit 17 in the previous stage is set as shown in FIG.
In the period indicated by A in g), a sample hole is used, and in the period indicated by B, a high-power resistance operational amplifier, etc. is used as is. It is supplied to the voltage follower circuit 19 at the subsequent stage.

Then, by passing through the voltage follower circuit 19, the error voltage Vp becomes a signal waveform as shown in FIG. 2(i), and resistors R,,R,,R.

The voltage is supplied to a loop filter 20 configured by F E T 2 , diodes DI and D2, a capacitor C2, an operational amplifier 20a, and a constant voltage source E2.

By the way, the pulse signal (C) outputted from the M-M 30 is inverted in polarity and supplied to FET2 in the loop filter 20, and the characteristics of the loop filter 20 are as shown in FIG. 2(g). During the period indicated by B, FET2 is ON, so the resistors Rr and R2 in the loop filter 20 are connected in parallel, the loop band of the loop filter 20 is expanded, and the pilot signal input to the PLL circuit is input in a short time. It becomes phase synchronized with fp.

In addition, the FET 2 is turned off except for the period indicated by B above, and the loop band of the loop filter 20 is set narrowly. Therefore, the PLL circuit does not follow fast phase changes, and the V
It is possible to prevent the clock signal fsc output from COIO from being phase-synchronized with the signal whose frequency is fpfnfH.

Then, the frequency of the clock signal fsc output from the VCOIO is controlled by the error voltage Vp passed through the loop filter 20 whose loop band is controlled as described above, and the clock signal fSC output from the CO is transmitted to the TBC circuit 7. supplied to

Then, in the TBC circuit 7, the supplied baseband image signal is digitized in synchronization with the clock signal fsc supplied from the VCOIO, and after being stored in a memory or the like,
Read from the memory in synchronization with an accurate lock signal,
By converting it again into an analog baseband image signal, the TBC circuit 7 outputs a baseband image signal from which time axis fluctuations have been removed.

In this embodiment, the loop gain of the loop filter is changed, but the capacitance of the capacitor C2 is made smaller during the period shown by B in FIG. 2(g), and the cabling range of the loop filter is expanded. Also good.

Furthermore, in this embodiment, the image signal is a monochrome image signal, but
The present invention can also be applied to devices that use color image signals, and similar effects can be obtained.

Furthermore, in this embodiment, the case where the present invention is applied to a playback device of an electronic still video system has been described, but the present invention is not limited to this, but can also be applied to a system such as a video tape recorder.

As described above, the sample-and-hold pulse supplied to the sample-and-hold circuit that samples and holds the error voltage Vp is the sample-and-hold pulse that is supplied to the sample-and-hold circuit that samples and holds the error voltage Vp obtained during the horizontal blanking period, and the sample-and-hold pulse that is supplied to the sample and hold circuit that samples and holds the error voltage Vp obtained during the horizontal blanking period. The resulting error voltage Vp is formed from a control pulse for supplying to the next-stage loop filter, and a clamp circuit is provided between the phase comparator and the sample-and-hold circuit, resulting in a simple circuit configuration.
It becomes possible to configure a PLL circuit in which the pilot signal fp can perform accurate and stable phase control without being phase-synchronized with a sideband wave having a frequency of fp±nf.

(Effects of the Invention) As described above, according to the present invention, it is possible to reliably and stably remove the time axis fluctuations of the image signal that occur during playback, and to generate an image signal with accurate time axis. It is possible to provide an image signal recording and reproducing system that can reproduce images.

[Brief explanation of drawings]

FIG. 1 is a diagram showing, as an embodiment of the present invention, a schematic configuration of a reproducing device in an image signal recording and reproducing system to which the present invention is applied. FIG. 2 is a timing chart showing signal waveforms at various parts in FIG. 1 for explaining the operation of the apparatus shown in FIG. 1. FIG. 3 is a diagram showing frequency allocation of a TBG-like reference signal that is frequency-multiplexed with an image signal during recording. FIG. 4 is a diagram showing a schematic configuration of a reproducing device in a conventional image signal recording and reproducing system. 8... Pilot signal separation circuit 9... Phase comparator 10... ■C. 11... Frequency divider 16... Band pass filter 17... Clamp circuit 18... Sample hold circuit 20... Loop filter 21... Inverter 22... 1/2H killer circuit 23. 25, 26, 29.30... Mono multivibrator 24.27... NAND gate 28... Vertical synchronization signal separation circuit

Claims (1)

[Claims] A system for recording a single-frequency pilot signal together with an image signal on a recording medium and reproducing the image signal recorded on the recording medium, comprising: recording means for adding a single frequency pilot signal and recording it on a recording medium; sampling clock generating means for generating a sampling clock signal for sampling an image signal separated from a signal reproduced from the recording medium; a phase comparison means for separating a pilot signal from a reproduction signal reproduced from a recording medium, comparing the phases of the separated pilot signal and the sampling clock signal, and outputting a phase error signal according to the phase comparison result; clamping means for clamping the phase error signal output from the phase comparison means and supplying the clamped phase error signal to the sampling clock generation means; and clamping means for sampling and holding the clamped phase error signal output from the clamping means. , sample and hold means for supplying the sampled and held phase error signal to the sampling clock generation means; first pulse signal generation means for outputting a first pulse signal corresponding to the vertical blanking period; and the first pulse signal generation. A second pulse signal for forming and outputting a clamp pulse signal for controlling a clamp operation in the clamp means and a sample hold pulse signal for controlling a sample hold operation for the sample hold means using the first pulse signal output from the means. pulse signal generating means; and control means for controlling the phase of the sampling clock signal generated by the sampling clock generating means using the phase error signal clamped by the clamping means and sampled and held by the sample holding means. An image signal recording and reproducing system characterized by comprising: