JPH0441357Y2

JPH0441357Y2 -

Info

Publication number: JPH0441357Y2
Application number: JP1987123432U
Authority: JP
Priority date: 1987-08-12
Filing date: 1987-08-12
Publication date: 1992-09-29
Also published as: JPS6430493U

Description

【考案の詳細な説明】（産業上の利用分野）本考案は、自動車用のデジタル時計に関する。[Detailed explanation of the idea] (Industrial application field) The present invention relates to a digital watch for automobiles.

（従来技術）従来から自動車用デジタル時計は特開昭52−
115026号に示すように時刻表示時、つまりACC
スイツチオン時のみ時刻修正が可能として、不必
要な修正が行なわれないように構成している。(Prior art) Digital clocks for automobiles have been developed since 1972.
As shown in No. 115026, when the time is displayed, that is, ACC
The configuration is such that the time can be adjusted only when the switch is turned on, so that unnecessary adjustments are not made.

（考案が解決しようとする問題点）しかしながら、時・分・秒の時刻桁のうち、
分・秒の修正は、現在の時計の精度からいつて使
用者が比較的ひんぱんに行うものであるが、時の
修正は自動車に時計を組み込んだとき、あるいは
電源としてのバツテリー交換時であり、その修正
回数は非常に少ない。したがつて従来のようにわ
ざわざ時修正用のスイツチを設けることは非常に
不経済であつた。(Problem that the invention attempts to solve) However, among the time digits of hours, minutes, and seconds,
The minutes and seconds are adjusted relatively frequently by users due to the accuracy of current clocks, but the time is adjusted when the clock is installed in a car or when replacing the battery as a power source. The number of revisions is very small. Therefore, it is extremely uneconomical to provide a switch for adjusting the time as in the past.

（問題点を解決するための手段）本考案は、修正スイツチとして２個のみ設け、
ACCスイツチオン時は、分修正用・秒リセツト
用として用いられ、ACCスイツチオフ時に、両
スイツチをオンした時に時の修正が為されるよう
にしたことを特徴とする。(Means for solving the problem) The present invention provides only two correction switches,
When the ACC switch is on, it is used to correct the minutes and reset the seconds, and when the ACC switch is off, the time is corrected when both switches are turned on.

（実施例）図面は本考案の一実施例を示す回路図であり、
図において、発振回路２、分周回路４、カウンタ
群６、デコーダ８、ドライバ１０、表示部１２は
通常のデジタル電子時計と同様の構成である。(Example) The drawing is a circuit diagram showing an example of the present invention.
In the figure, an oscillation circuit 2, a frequency dividing circuit 4, a counter group 6, a decoder 8, a driver 10, and a display section 12 have the same configuration as a normal digital electronic watch.

カウンタ群６は、秒カウンタ６ａ、分カウンタ
６ｂおよび時カウンタ６ｃから成り、ドライバ１
０の電源端子には第４のゲート回路１４を構成す
るオアゲートを介したACCスイツチ１６と修正
スイツチ群１８内の第１スイツチ１８ａの信号が
入力しており、スイツチ１６，１８ａのいずれか
のオン操作でドライバ１０は駆動可能になり、表
示部１２は点灯してカウンタ群６でカウントされ
た時刻が表示される。 The counter group 6 consists of a second counter 6a, a minute counter 6b, and an hour counter 6c, and the driver 1
The signals from the ACC switch 16 and the first switch 18a in the correction switch group 18 are input to the power supply terminal 0 through the OR gate constituting the fourth gate circuit 14, and when either switch 16 or 18a is turned on, The driver 10 becomes drivable by the operation, and the display section 12 lights up to display the time counted by the counter group 6.

修正スイツチ群１８は第２スイツチ１８ｂも有
し、これら第１および第２スイツチ１８ａ，１８
ｂはそれぞれ第１のゲート回路２０内のアンドゲ
ート２０ａ，２０ｂの一方の入力に接続される。
このアンドゲート２０ａ，２０ｂの他方の入力に
はACCスイツチ１６が接続されており、このア
ンドゲート２０ａ，２０ｂはACCスイツチオン
時、つまり表示部１２が点灯しているときに第１
および第２スイツチの操作信号を出力するように
構成されている。また第１スイツチ１８ａは第２
のゲート回路２２に入力している。この第２のゲ
ート回路２２は一方の入力にACCスイツチ１８
が直接接続され、他方の入力にインバータ２４を
介して第１スイツチ１８ａが出力されたノアゲー
ト２６から成るため、ACCスイツチ１６がオフ
時に、第１スイツチ１８ａの操作信号が出力され
るように構成されている。 The correction switch group 18 also has a second switch 18b, and these first and second switches 18a, 18
b are connected to one input of AND gates 20a and 20b in the first gate circuit 20, respectively.
The ACC switch 16 is connected to the other input of the AND gates 20a, 20b.
The second switch is configured to output an operation signal for the second switch. Also, the first switch 18a is
It is input to the gate circuit 22 of. This second gate circuit 22 has one input connected to the ACC switch 18.
is directly connected to the NOR gate 26, and the first switch 18a is outputted to the other input via the inverter 24. Therefore, when the ACC switch 16 is off, the operation signal of the first switch 18a is output. ing.

そしてこの第１および第２のゲート回路２０，
２２の出力信号は第３のゲート回路２８のアンド
ゲート２８ａ，２８ｂ，２８ｃの一方の入力にそ
れぞれ入力する。これらアンドゲート２８ａ〜２
８ｃの他方の入力には、オアゲート２８ｄを介し
たACCスイツチ１６および第２スイツチ１８ｂ
が接続されている。したがつてこのACCスイツ
チ１６あるいは第２スイツチ１８ｂがオンしてい
るときのみアンドゲート２８ａ〜２８ｃは開状態
となり、第２のゲート回路２２からの出力信号は
アンドゲート２８ａを介して時カウンタ６ｃに供
給可能となり、第１のゲート回路２０内のアンド
ゲート２０ａからの出力信号はアンドゲート２８
ｂを介して分カウンタ６ｂに、アンドゲート２０
ｂからの出力信号はアンドゲート２８ｃを介して
秒カウンタ６ａのリセツト端子に供給可能とな
る。 And these first and second gate circuits 20,
The output signals of 22 are input to one input of AND gates 28a, 28b, and 28c of the third gate circuit 28, respectively. These AND gates 28a-2
The other input of 8c is connected to the ACC switch 16 via the OR gate 28d and the second switch 18b.
is connected. Therefore, only when the ACC switch 16 or the second switch 18b is on, the AND gates 28a to 28c are open, and the output signal from the second gate circuit 22 is sent to the hour counter 6c via the AND gate 28a. The output signal from the AND gate 20a in the first gate circuit 20 is supplied to the AND gate 28.
b to minute counter 6b, and gate 20
The output signal from b can be supplied to the reset terminal of second counter 6a via AND gate 28c.

この結果、ACCスイツチ１６がオン時には、
第１スイツチ１８ａは分修正用として、１８ｂは
秒リセツト用として用いられ、ACCスイツチ１
６オフ時には第２スイツチ１８ｂをオンすれば、
第１スイツチ１８ａは時修正用スイツチとなる。 As a result, when the ACC switch 16 is on,
The first switch 18a is used to correct the minutes, the first switch 18b is used to reset the seconds, and the ACC switch 1
If the second switch 18b is turned on when 6 is off,
The first switch 18a serves as a time adjustment switch.

（考案の効果）このように本考案によれば、ACCスイツチオ
ン時に、つまり運転中にめつたに行なわない時修
正を、ACCオフ時に他の修正スイツチで行なえ
るように兼用したため、操作スイツチの数が減
り、コスト低減となる。またスイツチを減らした
ことによる修正のやりにくさも生じない。(Effects of the invention) As described above, according to the invention, the correction switch can be used to perform corrections when the ACC switch is turned on, that is, when it is not usually performed during driving, and when the ACC is turned off, so the number of operation switches is reduced. This reduces costs. Furthermore, the difficulty in making corrections due to the reduced number of switches does not arise.

[Brief explanation of the drawing]

図面は、本考案の実施例に係る自動車用デジタ
ル時計の回路図。６……カウンタ群、１４……第４のゲート回
路、１６……ACCスイツチ、１８……修正スイ
ツチ群、２０……第１のゲート回路、２２……第
２のゲート回路、２８……第３のゲート回路。 The drawing is a circuit diagram of a digital automobile watch according to an embodiment of the present invention. 6... Counter group, 14... Fourth gate circuit, 16... ACC switch, 18... Correction switch group, 20... First gate circuit, 22... Second gate circuit, 28... 3 gate circuit.

Claims

[Scope of utility model registration request]

An oscillator circuit, a frequency divider circuit that divides the frequency of this oscillation circuit, and a signal from this frequency divider circuit are counted and the time is calculated.
A counter group that counts minutes and seconds, a decoder that converts the count signal from this counter group into a display signal, a driver that amplifies the display signal from this decoder, and a display section that displays using the display signal from this driver. , an ACC switch, a correction switch group that supplies a correction signal to the counter group by external operation, and a correction control circuit that controls the correction signal from the correction switch group with an on/off signal from the ACC switch. In the modification switch group, the modification switch group is composed of a first switch and a second switch, and the modification control circuit is connected to the first and second switches, and only when the ACC switch is turned on, the modification control circuit receives the signal from the first and second switches. The first to pass the correction signal of
the gate circuit and the first switch are connected,
a second gate circuit that allows the correction signal from the first switch to pass only when the ACC switch is off; output signals of the first and second gate circuits are input; a third gate circuit for supplying the correction signal from the first gate circuit to the minute and second counter group and for supplying the correction signal from the second gate circuit to the hour counter group; An automobile watch comprising: a fourth gate circuit that outputs a drive signal for driving the driver when the second switch is turned on.