JPH0441377Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a timing signal generation circuit that generates a timing signal having a predetermined delay time and a predetermined pulse width with respect to a reference periodic signal. Specifically, it relates to improving timing errors.

(Prior Art) For example, in a type of timing signal generator used in an LSI tester, a predetermined delay time and a predetermined pulse width are set for each period of the reference period signal with respect to the reference period signal. There are timing signals that are configured to generate a timing signal in which a predetermined delay time is set with respect to the reference periodic signal for each cycle of the reference periodic signal, but the pulse width is set constant.

Figure 3 shows such a timing signal generator.
FIG. 2 is a configuration explanatory diagram showing an example of a TG. In FIG. 3, reference numeral 1 denotes a reference period signal generating section that outputs a reference period signal RATE having a constant period. 2 is a reference period signal RATE based on the reference period signal RATE.
A format clock FCLK in which a predetermined delay time Td and a predetermined pulse width W are set with respect to the reference periodic signal RATE for each period of
This is a format clock generator that outputs the following.
3 is a pulse width at which a predetermined delay time Td' is set for each cycle of the reference period signal RATE based on the reference period signal RATE.
W' is a strobe clock generator that outputs a constant strobe clock SCLK. Figure 4 shows
This is a timing chart showing an example of a signal output from such a timing signal generator TG, in which a indicates a reference period signal RATE, b indicates a format clock FCLK, and c indicates a strobe clock SCLK. There is.

Figure 5 shows such a timing signal generator.
FIG. 2 is a configuration explanatory diagram showing an example of a digital pattern generation device using TG. In FIG. 5, PG is a pattern data generator, and FMT is a format device. The pattern data generator PG outputs a digital signal DS as shown in FIG. 6b whose level changes with the period of the reference period signal RATE. For example, the format device FMT calculates the logical product of such a digital signal DS and the format clock FCLK as shown in FIG. 6c, and generates a digital pattern DP as shown in FIG. 6d on an object to be measured (not shown). Output to. As a result, the time relationship between the format clock FCLK and the reference periodic signal RATE can be arbitrarily set as described above, so that a digital pattern DP having a different time relationship can be obtained for each period of the reference periodic signal RATE. Note that the logical operation in the format device FMT may be, for example, an exclusive OR.
When the exclusive OR of the digital signal DS shown in FIG. 6b and the format clock FCLK shown in FIG. 6c is calculated, a digital pattern DP' as shown in FIG. 6e is obtained. Become.

By the way, conventionally, the format clock generating section 2 shown in FIG. 3 has been configured as shown in FIG. 7, for example. In FIG. 7, 4 is a down counter, and two are provided, one for setting delay time and one for setting pulse width. 5 is down counter 4
Delay time setting data DLD that should be preset to
This is a memory in which pulse width setting data PWD is stored. Reference numeral 6 indicates a plurality of control signals (for example, CS2
~CS4), and shows an example in which three delay circuits 7 to 9 having the same maximum nominal delay time TdS are connected in series. Here, the reason why multiple delay circuits are used is that a delay circuit with a short delay time has better rise characteristics than a delay circuit with a long delay time. For example, if a 200MHz counter clock CCLK is used, the cycle will be 5ns. Then, control signals CS1 to S
If the time difference between 4 and 4 is about 30 ns, it is sufficient to use one delay circuit with a delay time of about 30 ns and an intermediate output tap, but the rise time of such a delay circuit is about 10 ns. This may result in an error of several counts.
On the other hand, in the case of a delay circuit with a delay time of about 10 ns, the rise time will be about 3 ns,
Counting errors can be reduced. As a result, the down counter 4 loads the preset data DLD, PWD from the memory 5 in accordance with the control signal CS1 consisting of the reference period signal RATE and the control signals CS2 to CS4 output from the control circuit 6, and loads the preset data DLD and PWD from the memory 5. Count clock from DLD, PWD
Counts down according to CCLK. 10 is a numerical value detector that detects when the count value DLC, PWC of the down counter 4 reaches a predetermined value (for example, zero), and when the count value DLC related to the delay time reaches a predetermined value. By detecting that the delay time pulse DLP is detected, the pulse width pulse PWP is output by detecting that the count value PWC related to the pulse width reaches a predetermined value. 8 is a predetermined delay time with respect to the reference period signal RATE based on the delay time pulse DLP and pulse width pulse PWP added from the numerical detector 7.
This is a timing waveform forming circuit that forms a timing signal TS having Td and a predetermined pulse width W.

FIG. 8 is a timing chart for explaining the operation of FIG. 7, in which a indicates the reference period signal RATE, b indicates the delay time pulse DLP, c indicates the pulse width pulse PWP, d indicates the timing signal TS. That is, the delay time Td of the timing signal TS output from the timing waveform forming circuit 11 with respect to the reference period signal RATE is set by the delay time data DLD loaded from the memory 5 to the down counter 4, and the pulse width W is It is set by the pulse width data PWD loaded from the memory 5 to the down counter 4.

(Problem to be solved by the invention) However, according to such a configuration, the control circuit 6
is constructed by connecting delay circuits 7 to 9 in series, so delay errors due to variations in the characteristics of these delay circuits 7 to 9 are sequentially integrated as shown by the broken line in FIG. 9, and the control signal CS1 A time error will occur between S4 and S4. In addition, the 9th
In the figure, a indicates the input of the delay circuit 7, b indicates the output of the delay circuit 7, c indicates the output of the delay circuit 8, and d indicates the output of the delay circuit 9. Such a time error may be caused by insufficient time margin inside the down counter 4 or by the down counter 4.
This is undesirable because it increases the number of adjustment steps.

The present invention focuses on these points, and its purpose is to reduce the influence of delay errors due to variations in the characteristics of the delay circuit, increase the time margin inside the down counter, and improve the adjustment of the down counter. An object of the present invention is to provide a timing signal generating device that does not require a timing signal.

(Means for Solving the Problems) The present invention that achieves the above object establishes a predetermined time relationship for each cycle of the reference cycle signal and the reference cycle signal output from the control circuit. It has two down counters whose operation is controlled by a plurality of control signals, and has a timing having a predetermined delay time and a predetermined pulse width with respect to a reference periodic signal according to the output signals of these down counters. The timing signal generating device for generating a signal is characterized in that the control circuit is constituted by a series circuit of a delay circuit, a down counter, and a latch circuit driven by a common clock.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention, and the same parts as in FIG. 7 are given the same reference numerals. The difference between FIG. 1 and FIG. 7 is the control circuit 6.
This is the part. That is, in the control circuit 6 of FIG. 1, 12 and 13 are latch circuits driven by the counter clock CCLK common to the down counter 4. Here, latch circuit 12 is connected in series between delay circuits 7 and 8, and latch circuit 13 is connected in series between delay circuits 8 and 9. Note that the operations of the other circuits except for the selection signals CS2 to CS4 outputted from the control circuit 6 are the same as those shown in FIG. 7, so a re-explanation thereof will be omitted.

In such a configuration, the delay circuit 7 delays the reference periodic signal RATE by a predetermined time (for example, TdS) and applies it to the latch circuit 12. This latch circuit 1
2 synchronizes the output of the delay circuit 7 with the operation of the down counter 5. The output of the latch circuit 12 is delayed by a predetermined time (for example, TdS) in the delay circuit 8 and then applied to the latch circuit 13. This latch circuit 13 converts the output of the delay circuit 8 into a down counter 5.
It will be synchronized with the operation of Then, the output of the latch circuit 13 is sent to the delay circuit 9 for a predetermined time (for example,
TdS) delayed. That is, the output of the delay circuit 7 is latched by the latch circuit 12 to match the timing and then input to the delay circuit 8, and the output of the delay circuit 8 is latched by the latch circuit 13 to match the timing and then input to the delay circuit 9. are doing. Therefore, delay errors due to variations in the characteristics of the delay circuits in the preceding stage do not affect the subsequent stage.

As a result, the time errors of the delay circuits are not accumulated sequentially as in the conventional case, and can be suppressed to the time errors of a single delay circuit.

FIG. 2 is a timing chart for explaining the operation of the control circuit 6 shown in FIG. 1. As shown in FIG.
In FIG. 2, a indicates the input of the delay circuit 7,
b indicates the input of the latch circuit 12, c indicates the input of the latch circuit 13, and d indicates the output of the delay circuit 9.

By configuring like this, the control signal CS
The influence of time errors that CS2 to CS4 receive due to variations in the characteristics of delay circuits 7 to 9 can be suppressed to the time error of the delay circuit alone, and the lack of time margin inside the down counter 4 as in the conventional case can be avoided. This does not result in an increase in the number of man-hours required for adjusting the down counter 4.

Incidentally, the inputs of the latch circuits 12 and 13 may be taken out from the intermediate taps of the delay circuits 7 and 8 at the previous stage, respectively.

Further, the timing signal generating device configured in this manner can also be applied to various devices using counters.

(Effects of the invention) As explained above, according to the invention, the influence of delay errors due to variations in the characteristics of the delay circuit can be reduced, so the time margin inside the down counter is large and there is no need to adjust the down counter. This makes it possible to realize a timing signal generating device that is highly effective in practical use.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention;
FIG. 2 is a timing chart for explaining the operation of the main parts of FIG. 1, FIG. 3 is a configuration explanatory diagram showing an example of a timing signal generator to which the present invention can be applied, and FIG. 4 is the operation of FIG. 3. 5 is a configuration explanatory diagram showing an example of a digital pattern generator using the device shown in FIG. 3. FIG. 6 is a timing chart for explaining the operation of FIG. 7 is a configuration explanatory diagram showing a conventional example of the format clock generating section in FIG. 3, FIG. 8 is a timing chart for explaining the operation of FIG. 7, and FIG. 9 is a main part of FIG. 7. This is a timing chart for explaining the operation. 4...Down counter, 5...Memory, 6...
control circuit, 7-9... delay circuit, 10... numerical value detector, 11... timing waveform forming circuit, 12,
13...Latch circuit.

Claims (1)

[Scope of utility model registration request] It has two down counters whose operations are controlled by a plurality of control signals having a predetermined time relationship with respect to the reference period signal and the reference period signal output from the control circuit for each period of the reference period signal, and In a timing signal generation circuit that generates a timing signal having a predetermined delay time with respect to a reference periodic signal and a predetermined pulse width according to an output signal of a down counter, the control circuit includes a delay circuit and a down counter. 1. A timing signal generation circuit comprising a series circuit with a latch circuit driven by a common clock.