JPH0441383B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interface device for inputting digital signals used in a computer system using interrupt signals.

[Conventional technology]

FIG. 3 is a block diagram of a conventional example of an interface device for a digital circuit using an interrupt signal.
The operation of this conventional example will be explained below with reference to the time chart of FIG.

Now, when the state of the input signal S _I1 changes at time _t1 , a detection signal is output from the state change detection circuit 21 to the OR circuit 23, and this detection signal is further input to the set input terminal S of the flip-flop 24.
An interrupt signal _{S_INT} is output from the output terminal Q of the flip-flop 24. After the external device that received this interrupt signal S _INT outputs an interrupt reset signal S _IR to the reset terminal R of the flip-flop 24,
When the data read signal S _R was output at time t ₂ , this data read signal S _R served as an enable signal for the buffers 25 and 26, and the output signals S _p1 and S _p2 were read out.

[Problem that the invention seeks to solve]

In the conventional interface device mentioned above, the time
Assuming that the state of the input signal S _I2 changes at t ₂ and the output signal S _p2 is read out according to the input signal S _I2 after the change, the interrupt signal S _INT is output based on the state change of the input signal S _I2 . , an interrupt reset signal S _IR and a data read signal S _R are generated, and the output signals S _p1 and S _p2 read out at time t ₂ are read out again at time t ₃ , resulting in a wasteful operation. .

SUMMARY OF THE INVENTION An object of the present invention is to provide an interface device that does not cause unnecessary operations such as repeating the same data read twice even if the input signal changes at the same time as the data is read.

[Means for Solving the Problem] The interface device of the present invention connects a first input signal to an input terminal of a first latch circuit and one input terminal of a first comparison circuit, and The output terminal of the latch circuit is connected to the input terminal of the first buffer and the other input terminal of the first comparison circuit, and the second input signal is connected to the input terminal of the second latch circuit and the other input terminal of the second comparison circuit. The output terminal of the second latch circuit is connected to the input terminal of the second buffer and the other input terminal of the second comparison circuit. The first and second buffers are controlled by a data read signal, the output terminals of the first and second buffers are used as first and second output signals, respectively, and the first and second buffers are controlled by a data read signal.
The output terminal of the comparison circuit is connected to the input terminal of an OR circuit, and the interrupt signal is obtained from the output terminal of the OR circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an interface device according to an embodiment of the present invention. Latch circuit 11,1
2 holds the input signals S _I1 and S _I2 , respectively, when the data read signal S _R is input from an external device. Buffers 13 and 14 are data read signals from external devices.
When inputting S _R , latch circuits 11 and 12 respectively.
The contents held by the controller are outputted to external devices as output signals S _p1 and S _p2 . Comparing circuits 15 and 16 input and compare the input signal S _I1 and the output signal of the latch circuit 11, and the input signal S _I2 and the output signal of the latch circuit 12, respectively, and when the two levels are equal, the level is low, and when they are different, the level is low. Outputs a high level signal to.
The OR circuit 17 takes the logical sum of the respective output signals of the comparison circuits 15 and 16, and outputs the result as an interrupt signal _{S_INT} .

The operation of this embodiment will be explained below with reference to the time chart of FIG.

As an example, in the initial state, the input signal and output signal of the latch circuit are at the same level. That is, the output signal of latch circuit 11 = input signal S _I1 , latch circuit 1
2 output signal=input signal S _I2 . Therefore, the comparison circuit 15 compares the output signal of the latch circuit 11 and the input signal S _I1 and sets it to high level if they do not match.
The output of is low level. Similarly, latch circuit 1
The output of the comparison circuit 16, which compares the output signal of No. 2 and the input signal S _I2 and sets it to high level if they do not match, is at low level. Therefore, the output of the OR circuit 17, which receives the outputs of the comparison circuits 15 and 16 as input, becomes a low level, and the interrupt signal _SINT , which becomes a high level when in an interrupt notification state, is at a low level and is not in an interrupt notification state to an external device. Show that.

Also, if the data read signal (active high) from the external device is low level, the buffer 1
The state of each output S _p1 and S _p2 of No. 3 and No. 14 is undefined.

Next, when the level of the input signal S _I1 changes to high level at time _t4 , the output signal (low level) of the latch circuit 11 and the level of the input signal S _I1 (high level) are different, so the comparator circuit 15 A high level signal is output, and a high level interrupt signal S _INT is outputted to an external device via the OR circuit 17. Then, when the external device outputs the data read signal S _R (high level) at time _t5 , the latch circuits 11 and 12 hold the input signals S _I1 and S _I2 , respectively, at the rising edge of the data read signal S _R , and the buffer 13,14
, the output signals of the latch circuits 11 and 12 are output signals while the data read signal S _R is at high level.
It is output as S _p1 and S _p2 and read out to an external device.
In addition, the latch circuits 11 and 12 each receive an input signal.
By holding S _I1 and S _I2 , the comparator circuit 15,
Since the levels of each of the two inputs of 16 become equal, the interrupt signal S _INT falls to a low level at time t ₅ .

By the way, as shown in Fig. 2, the data read signal S _R
At time _t5 when the input signal S I2 is output, the level of the input signal S _I2 changes to low level, and the data read signal S _R after the change
Even if the output signal S _p2 is read out according to the input signal S _I2 (low level), the data read signal S _R
Since the latch circuits 11 and 12 that input the input signal S I1 and S I2 respectively hold the input signals S _I1 and S _I2 ,
The levels of each of the two inputs of 6 become equal, and the interrupt signal S _INT falls at time t ₅ .

On the other hand, at time _t5 , when the level of the input signal S _I2 changes to low level and the data read signal S _R rises before that change, the output signal of the latch circuit 12 remains at high level, and the input signal S I2 changes to low level. Signal S _I2
is low level, the output of the comparison circuit 16 is high, that is, the interrupt signal is passed through the OR circuit 17.
S _INT remains at a high level.

With the above, the external device receives the latest input signal S _I1 ,
If the state of S _I2 is read, the interrupt signal S _INT becomes low level, and conversely, if it is not read, the interrupt signal S _INT becomes high level. Therefore, reading of the same data is not repeated twice.

〔Effect of the invention〕

As described above, according to the present invention, even if the state of an input signal changes at the same time as data is read, the same data is not read repeatedly, and unnecessary operations can be omitted.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an interface device according to an embodiment of the present invention, FIG. 3 is a block diagram of an interface device according to a conventional example, and FIGS. 2 and 4 are FIGS. 1 and 3, respectively. This is a time chart of the interface device. 11, 12... Latch circuit, 13, 14... Buffer, 15, 16... Comparison circuit, 17... OR circuit, S _I1 , S _I2 ... Input signal, S _p1 , S _p2 ... Output signal, S _R ...Data read signal, S _INT ...Interrupt signal.

Claims (1)

[Scope of Claims] 1. An interface device that outputs an interrupt signal to an external device, inputs a data read signal from the external device, and outputs data to the external device, comprising: a plurality of latch circuits each holding an input signal; a plurality of buffers each inputting each output signal of the plurality of latch circuits in response to the data read signal and outputting a plurality of output signals; and the plurality of input signals. and each output signal of the plurality of latch circuits, and outputs a signal indicating a mismatch state if the two are different from each other, and at least one of the plurality of comparison circuits An interface device comprising: a logic circuit that outputs the interrupt signal when the signal is output.