JPH0441392Y2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a debugging device for evaluating a program before it is written into a one-chip microcomputer for mass production.

(b) Conventional technology In general, one-chip microcomputers are
It has a built-in ROM (read-only memory) that stores programs, and programs created by the user or the like are written using a mask when the one-chip microcomputer is manufactured.
Therefore, when developing a program, or
When evaluating a program, a debugging device is used that uses a microcomputer called an evaluation chip, which has substantially the same functions as a one-chip microcomputer for mass production.

By the way, conventional evaluation chips have, in addition to the input/output terminals of mass-produced one-chip microcomputers, terminals for applying instruction codes from the outside, terminals for outputting data from internal program counters, etc. , various control terminals are provided. When evaluating a program, the program stored in the memory circuit of the debugging device is sequentially read out, an instruction code is applied to the terminal of the evaluation chip to execute it, and the result is sent to the input/output terminal or to the internal RAM. The data is read out and the operation is checked.

The above is described in the microcomputer data series No. 3 "LM6499 Manual" published by the applicant on February 15, 1980.

(c) Problems to be solved by the invention However, when the above-mentioned evaluation chip is used, it is not possible to check the flag status by displaying it on a display device, for example, so it is not possible to check the flag operation. The only way to determine this was from the data retrieved by executing the subsequent program. On the other hand, in order to output the output of the flag to the outside, a dedicated evaluation chip must be prepared which is provided with the output terminal, which has the drawback that it takes time to design.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and includes a program storage circuit that provides instruction codes to an evaluation chip, and a program storage circuit that supplies instruction codes to an evaluation chip. an instruction decoder to which instructions given to the chip are applied simultaneously and decodes flag set or reset instructions; a plurality of flip-flops to which flag set and reset signals outputted from the instruction decoder are applied; This debugging device is equipped with a plurality of display circuits that display the contents of a flip-flop, and the flag state of the evaluation chip can be monitored by the display state of the display circuit.

(E) Effect According to the above-described means, when a flag set or reset instruction is retrieved from the program storage device during debugging of a program, this set or reset instruction is applied to the evaluation chip and also debugged. Applied to an instruction decoder within the device. When the set command or reset command is decoded in the instruction decoder, a set signal or a reset signal is generated, and the corresponding flip-flop is set or reset. The output of this flip-flop is displayed by a display circuit.

(F) Embodiment The figure is a circuit diagram showing an embodiment of the present invention, in which 1 is an evaluation chip, 2 is a program storage circuit, 3 is an instruction decoder, 4,
5, 6, 7 are flip-flops, 8 is a display circuit,
9 is an initial setting circuit.

The evaluation chip 1 is provided with an external terminal to which an instruction code is applied, and the external terminal is connected to an instruction bus 10 from a program storage circuit 2. The program storage circuit 2 is composed of, for example, an EPROM or the like, and has a program to be evaluated prepared in advance written therein, and the output of the program storage circuit 2 is connected to the instruction bus 10. The instruction bus 10 is composed of 8 bits and is also connected to the instruction decoder 3. The instruction decoder 3 includes AND gates 11 and 12 that input the upper 4 bits IR4 to IR7 of an 8-bit instruction code to detect whether it is a flag set instruction or a reset instruction, and It has AND gates 13 to 20 that control the sending of a set detection signal F _SET or a reset detection signal F _RES to set or reset the flag specified by 4 bits IR0 to IR3.
The outputs of the AND gates 13 to 20 are applied as a set signal SET or a reset signal RES to each set input S and reset input R of flip-flops 4, 5, 6, and 7, which are flags. The display circuit 8 includes driver N-channel MOSFETs 21 to 24 controlled by each output Q of the flip-flops 4, 5, 6, and 7;
It is composed of LEDs 25 to 28 driven by MOSFETs 21 to 24. Therefore, if the outputs of flip-flops 4 to 7 are "0", LED 25
to 28 do not emit light and are “1” when the LED 25
28 to 28 emit light. On the other hand, the initial setting circuit 9 receives the initial clear signal INT applied to the evaluation chip 1, and according to the signal INT, sets the flip-flops 4 to 7 to the same initial state as the flags in the evaluation chip 1. This is a circuit that does this.

Therefore, in the figure, when debugging a program, the address of the program storage circuit 2 is specified, the instruction code is read out, and the evaluation chip 1 and instruction decoder 3 are debugged.
to be applied. At this time, the address data is data taken out from the program counter of the evaluation chip 1, or data from a program counter (not shown) provided in the debugging device. Next, if the instruction code read from the program storage circuit 2 is a flag set instruction "11110010", the AND gate 11 output _FSET of the instruction decoder 3 becomes "1", and IR1 is applied. AND gate 1
The output SET of 7 becomes “1”. Therefore, the flip-flop 6 is set, and its output Q turns on the MOSFET 23, causing the LED 27 to light up. This confirms that the flag specified by IR1 is "1". When the flag reset command "11100010" is read in this state, the AND gate 12 output F _RES of the instruction decoder 3 becomes "1", and the output RES of the AND gate 18 to which IR1 is applied becomes "1". Therefore, the flip-flop 6 which was in the set state is reset. Therefore, MOSFET 23 is turned off by the output "0" of flip-flop 6.
The LED 27 goes out, confirming that the flag specified by IR1 has been reset.

In this way, the LED
The states of the flags of the evaluation chip 1 can be monitored by the lighting and non-lighting states of 25 to 28.

(g) Effects of the invention As described above, according to the invention, there is no need to design and manufacture an evaluation chip equipped with a dedicated terminal for flag monitoring, and the flags can be monitored by the debugging device itself. It is effective for evaluation and allows debugging in a short period of time. Therefore, it has the advantage of shortening the period from program creation to production of a one-chip microcomputer.

[Brief explanation of drawings]

The figure is a circuit diagram showing an embodiment of the present invention. Explanation of main figure numbers, 1...Evaluation chip, 2...Program storage device, 3...Instruction decoder, 4, 5, 6, 7...Flip-flop, 8...Display circuit, 9... Initial setting circuit.

Claims (1)

[Scope of utility model registration request] In a debugging device that evaluates a program using a one-chip microcomputer for mass production and an evaluation chip having substantially the same functions, the program storage circuit provides instruction codes to the evaluation chip, and the program storage circuit. Instructions given from the circuit to the evaluation chip are simultaneously applied, and an instruction decoder that decodes the flag set or reset instruction and a flag set and reset signal output from the instruction decoder are applied. The instruction decoder includes a plurality of flip-flops and a plurality of display circuits for displaying the contents of the flip-flops, and the instruction decoder generates a detection signal for setting or resetting a flag based on a predetermined bit of the instruction code;
The flag is specified based on the remaining bits of the instruction code, and the flip-flop corresponding to the specified flag is set or reset based on the detection signal, and the instruction code for indicating the state of the flag is specified. A debugging device for a microcomputer, characterized in that the state of the flag obtained by decoding is monitored by the plurality of display circuits.