JPH0441509B2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to a method for manufacturing a solid-state imaging device, and particularly to a method for manufacturing a solid-state imaging device, and in particular, a method for suppressing variations between pixels of a gate accumulation type static induction transistor image sensor and at the same time eliminating surface irregularities. The present invention relates to a manufacturing method for flattening and effectively letting in light.

Description of Prior Art Conventionally, there are CCD type and MOS type fixed imaging devices that have been put into practical use. Recently, a static induction transistor (StaticInduction) was proposed according to the present invention.
Transistor (SIT) type image sensors.
(IEEE Trans. on Eletron Devices, Vol ED−
26, No.12 (Dec.1979) pp1970-1977 and JP-A-Sho
58-105672).

The present inventors have also made various basic applications in matrix operation as applications in conjunction with the proposal of the basic structure. Regarding the specific manufacturing method, the invention is disclosed in JP-A-59-107582, JP-A-59-107583 and JP-A-59-108372. JP-A-59-107582 relates to a method for manufacturing an SIT image sensor having the simplest planar structure, and FIG. 1 shows the main parts of the manufacturing process. The prior art will be explained below based on the drawings. In FIG. 1, (A) After forming an n ^- buried layer 2 on an n ⁺ substrate or a p ^- substrate 1, a high resistance n ^- epitaxial film 3 is grown (in the example shown, n ^- , p ^- , Next, a field oxide film 7 is formed, and then boron is deposited and driven into the control gate portion 6 by ion implantation or diffusion. Next, boron is deposited and driven into the shielding gate portion 4 by ion implantation or diffusion using a mask.

(B) A mask alignment process (photolithography technique) is used to open a window in a predetermined source region 5, and phosphorus or As-doped polysilicon 8 is formed.
or by CVDing non-doped polysilicon 8, doping with phosphorus or arsenic and performing drive-in.

(C) Mask alignment (photolithography technology)
After etching the source electrode portion 8 and polysilicon leaving the source electrode portion 8 and the wiring portion 8, a PSG film 9 is formed by CVD.

(D) After etching and removing the field oxide film 7 and PSG 9 film on the upper part of the control gate portion 6 by mask alignment, the nitride film 10 is removed.
CVD and CVD of the transparent electrode SnO ₂ 11 are performed to form a storage MIS capacitor above the control gate portion 6.

(E) Only the upper part of the control gate part 6 and the wiring part SnO ₂ film 11 are left by the mask alignment and etching process, and a contact hole to the shielding gate part 4 is opened.

Finally, Al vapor deposition and wiring etching are performed.
The Al electrode 12 is in contact with the SnO ₂ electrode. The Al electrode 13 is an Al electrode for contact with the shielding gate portion 4. As is clear from the above explanation, the manufacturing method disclosed in JP-A No. 59-107582 requires seven masks excluding passivation, and the n ⁺ source portion 5,
The shielding gate portion 4 and the control gate portion 6 are formed using separate masks through separate mask alignment processes. In response to this manufacturing method, the present inventors proposed a self-alignment process for SIT image sensors in which a single mask is used to define the n ⁺ source portion 5 and the p ⁺ gate portions 4 and 6, and The final cross-sectional structure shown in No. 107583 is shown in Figure 2.

Next, the manufacturing process of the device shown in FIG. 2 will be briefly described. On n ⁺ substrate or p ^- substrate 1
After forming the n ⁺ buried layer 2, the n ^- high resistance epitaxial growth 3 (n ^- , p ^- , i in the illustrated example,
After (any method is possible), regions to become the source portion and gate portions 4 and 6 of the SIT are simultaneously defined using the LOCOS technique. That is. SIT source part 5,
LOCOS except for gate parts 4 and 6
It is covered with a thick oxide film 7. After the mask alignment step, the Si ₃ N ₄ film on the regions 4 and 6 that are to become the gate portions is removed, and the gate portions 4 and 6 of the SIT are removed by boron B ion implantation and heat treatment.
form 6.

Next, after the mask alignment process, the Si ₃ N ₄ film and the SiO ₂ film on the region 5 that is to become the source portion are removed,
An n ⁺ doped polysilicon 8 is formed on the entire surface by CVD technology, and an n ⁺ source diffusion region 5 is formed by a heat treatment process. The n ⁺ polysilicon 8 is etched to form a wiring portion. Next, CVD the PSG film
After the growth, the SiO ₂ film on the control gate region 6 is removed by a mask alignment process. After a Si ₃ N ₄ film 10 of a desired thickness is formed on the entire surface by CVD technology, a SnO ₂ film 11 is further grown by CVD. the above
An MIS structure is formed on the control gate 6 using the SnO ₂ 11/Si ₃ N ₄ 10/Si(p ⁺ )6 structure.
After etching the SnO ₂ film 11, a contact hole to the shielding gate portion 4 is opened,
Perform Al vapor deposition sintering. Excluding passivation, seven masks are required for the Al electrode wirings 12 and 13.

In the manufacturing process of the pixel of the SIT image sensor having the structure shown in FIG. 2, the positions of the source 5, gates 4 and 6 are defined by the first mask;
Compared to the manufacturing method shown in FIG. 1, variations between the source and gate can be suppressed. However, the first
The number of masks required for both the method shown in the figure and the method shown in FIG. However, this is because the diffusion steps for the gates 4, 6 and the source 5 are performed using separate masks, and the same mask is used when etching the SnO ₂ film 11 on the control gate 6 later. Because there are many people, the number of masks is the same. Since the formation of the gate portions 4 and 6 and the formation of the source portion 5 are performed in separate heat treatment steps, there is a drawback that the variation in the diffusion depth of the gate and the source increases, making it more vulnerable to variation in characteristics. In particular, variations in diffusion depth lead to variations in voltage amplification factor μ, which has the disadvantage of increasing variations in output characteristics.

The present inventors further disclosed another method for manufacturing an SIT image sensor in Japanese Patent Laid-Open No. 108372/1983. The cross-sectional shape of the final device is shown in FIGS. 3A and 3B. A feature of the manufacturing method shown in this figure is that LOCOS or plasma etching technology and LOCOS technology are used to form the shielding gate portion 4 deeply. 4. Deep p ⁺ in control gate part 6 using LOCOS technology
This is an example of diffusion of gates 4 and 6.
The position of the n ⁺ source region 5 is determined by mask alignment. That is, self-alignment
It's not that it's been digitized. In the structure shown in FIG. 3B, the p ⁺ gate diffusion 4 is deeply formed in the shielding gate portion 4 using plasma etching and LOCOS technology, and the p ⁺ control gate diffusion 6 is positioned and the n ⁺ source portion 5 is diffused. Positioning is performed by mask alignment using separate masks.

In FIG. 3A, the total number of masks is 7 excluding the passivation, and in FIG. 3B, the total number of masks is 7 to 8.

The manufacturing method of the SIT image sensor already disclosed and proposed by the present inventors is as described above.
There is a street. In the manufacturing method shown in Figure 1, the gate diffusion and source diffusion of the SIT are positioned by a mask alignment process using separate masks, so when arranging a large number of cells in a matrix, the sensitivity between pixels The drawback is that the characteristics have a large effect on variations. However, the final structure of the device is planarized, which is advantageous in terms of increasing light reception efficiency. In the manufacturing method explained in Fig. 2, the positions of the gate and source of the SIT are defined by the first mask, so dimensional variations are much suppressed compared to the method shown in Fig. 1. However, between the SIT gate and source
There is a thick oxide film created by the LOCOS process,
Light transmission into the SIT channel is poor. Also
The device surface has an uneven shape due to the influence of the oxide film caused by LOCOS, and the uneven shape scatters light, resulting in a structure that makes it difficult for light to enter the device effectively. Furthermore, since gate diffusion and source diffusion are ultimately performed using separate mask alignment, the total number of masks is seven, which is the same as in the case of FIG. In the manufacturing method explained in Figure 3A, p ⁺ gate diffusion is performed under the thick LOCOS oxide film at the same time as the LOCOS technology oxidation, so the light receiving surface is uneven and the source region is mask aligned. The positioning of the source diffusion regions is determined by the following method, and variations in the positions of the source diffusion regions have a large influence on the variations in the characteristics of the final devices arranged in plurality. Furthermore, as explained in Figure 3B
In the manufacturing method of SIT image sensors, the positioning of control gate diffusion and source diffusion is performed by a mask alignment process, which tends to cause variations in channel width dimensions and between source and gate dimensions, which makes it difficult to process multiple cells. If they are arranged in a matrix, this will greatly affect the variation in characteristics of each pixel.

As explained above, in the conventional technology already disclosed by the present inventors, in the method shown in FIGS. Both of these are determined separately, so when a plurality of cells are integrated, the characteristics of each pixel vary, making it difficult to increase the capacity (large number of pixels).

In addition, with the method shown in Figure 2, the device surface becomes uneven, and the source and gate diffusions are performed separately, resulting in variations in diffusion depth, resulting in variations in voltage amplification factor for each pixel, and The drawback was that the absorption efficiency was poor.

Furthermore, when considering the total number of masks, the number is 7 to 8 in all of the preceding examples shown in FIGS. 1, 2, and 3A and B.

An object of the present invention is to simultaneously arbitrarily determine a gate portion and a source portion when forming a pixel of a SIT image sensor, and to form gate and source diffusion regions in the same heat treatment process. This is to suppress variations in depth, variations in dimensions between pixels, variations in voltage amplification factor μ, and variations due to process conditions.

Another object of the present invention is to provide a method for manufacturing a SIT image sensor that forms a shallow source diffusion region of approximately 0.5 μm or less, increases sensitivity particularly to short wavelength light, and is highly reliable and operates at high speed. It is.

Another object of the present invention is to provide a method for manufacturing an SIT image sensor that suppresses variations between pixels, reduces noise due to variations, and easily increases capacity.

Still another object of the present invention is to reduce the number of required masks by one or two, excluding passivation, compared to conventional methods.
An object of the present invention is to provide a method for manufacturing a SIT image sensor.

Still another object of the present invention is to provide a method for manufacturing a gate accumulation type SIT image sensor in which the surface of the device is completely flattened and the light absorption efficiency is good.

Still another object of the present invention is to provide a method for manufacturing a SIT image sensor in which the number of heat treatment steps associated with diffusion is reduced by one time, thereby simplifying the manufacturing method.

Furthermore, another object of the present invention is to increase the sensitivity of each pixel when the distance between the gate part and the source part of the SIT image sensor and the channel dimensions are determined by the same mask, and when a plurality of SIT image sensors are arranged in a line or matrix. An object of the present invention is to provide a method for manufacturing a low-noise SIT image sensor with uniform characteristics.

The method for manufacturing a solid-state imaging device according to the present invention will be described in detail below.

Summary of the Invention As the configuration of the present invention, what kind of technical means constitutes the above object will be described in general.

(1) High-resistance epitaxial growth after forming an n ⁺ buried layer on an n ⁺ substrate or a p ^- substrate (with impurity density in the range of about 1×10 ¹² to 1×10 ¹⁴ cm ^-3 )
After that, the entire surface is oxidized. The thickness of the field oxide film is approximately 5,000 to 8,000 mm.
Next, a first mask alignment step is performed to open windows into the shielding gate portion, control gate portion, and source portion of the SIT image sensor. Next, N ⁺ polysilicon doped with As as an impurity is formed on the entire surface by CVD etc.
Furthermore, a PSG film is grown using CVD technology.

(2) Next, through a second mask alignment process, only the doped polysilicon and PSG films on the source portion are left, and the PSG film and doped polysilicon layer on the areas that will become the control gate and shielding gate are removed using plasma. Remove by etching etc.

(3) Next, boron ions are implanted over the entire surface to form p ⁺ diffusion layers in the shielding gate and control gate portions. At this time, in the heat treatment step after ion implantation, As is also diffused from the doped polysilicon into the Si layer at the same time, forming a source n ⁺ region.

(4) Next, after forming the PSG film again on the entire surface, the third
Through the mask alignment step, a window is opened in the control gate region and the p ⁺ control gate Si layer is exposed.

(5) Next, perform CVD or dry oxidation of a Si ₃ N ₄ film on the entire surface, and then form a transparent electrode such as SnO ₂ or ITO (indium oxide/tin oxide) film using CVD or other techniques. , forming a storage capacitor region of MIS structure on the control gate.

(6) After plasma etching the SnO ₂ electrode leaving only the SnO ₂ film at a predetermined location, a contact hole to the shielding gate portion is opened (fourth and fifth mask alignment steps).

(7) Form an Al electrode on the entire surface by vapor deposition, and contact the shielding gate area with Al and
A contact may be made in the SnO ₂ portion, and in some cases, a contact hole may be formed to the polysilicon layer in step (6), and then contact between Al and polysilicon may be made. After full surface sintering, CVD growth of Si ₃ N ₄ film is performed and final passivation is performed. (Sixth and seventh mask alignment steps).

The above is an overview of the present invention, and the cross-sectional shape of the final device is the same as that shown in FIG. However, compared to the manufacturing process shown in Figure 1, the number of masks is saved by one, and the distance between the shielding gate and the source and the distance between the control gate and the source can be positioned simultaneously in the first mask alignment process. Because gate and source diffusion are performed in the same heat treatment,
It has the advantage that there is almost no variation between pixels.

As is clear from the above explanation, according to the present invention
The SIT image sensor manufacturing method is very suitable for the manufacturing process of large-capacity area sensors in which a large number of cells must be manufactured uniformly and with the same sensitivity characteristics. Moreover, since the manufactured device is flattened, the light absorption efficiency is also good. The manufacturing process according to the present invention may be referred to as a planarization self-alignment process.

Due to the gate accumulation operation manufactured according to the present invention
The operation of the SIT image sensor is similar to the conventional example, with the SIT having a capacitor at the gate serving as one pixel.
It is similar to the conventional example in that the readout method is based on the Y-address method, and that a shielding gate using pn junction isolation is provided to isolate each pixel. Source side n ⁺ region 5,
Although the buried n ⁺ region is referred to as a drain here, region 2 may always be at ground potential and a video voltage is applied to wiring portion 8 of region 5. However, devices realized using conventional manufacturing methods tend to have uneven surfaces due to LOCOS and lack a self-assemble process, which tends to cause variations in the sensitivity characteristics of each pixel, as well as large fixed pattern noise, especially for large capacitors. Image sensor (500×700
Since uniformity is important, it was unsuitable for applications (including pixels). According to the present invention, it is possible to provide an image sensor in which each pixel is made uniform by a large-capacity planarization self-alignment process.

Next, the manufacturing process of the present invention will be explained based on the drawings.

FIG. 4 shows manufacturing steps A to G of an embodiment of the present invention, and each step will be explained in order. Each item below corresponds to the manufacturing process.

(A) The plane orientation of the substrate is good for both 111 and 100, and a common buried layer 2 is formed on the p ^-substrate 1 by diffusion or ion implantation of As or Sb, etc. in the area that will become the sensor area of the SIT image sensor. . In the buried layer 2, a common electrode is provided around the sensor area or at a predetermined portion. This electrode portion is either not shown in FIG. 4A or serves as a common drain region of multiple SIT matrices of the SIT image sensor. The reason for forming such a buried layer 2 is that the driving and scanning circuit for the matrix of the pixel portion of the SIT image sensor is to be formed on the same substrate 1.

Next, the high resistance epitaxial growth layer 3 is
Do this for about 5μ to 10μ. The conductivity type of this epitaxial growth layer 3 may be either n ^- or p ^- . It may also be an i-layer. Next, perform wet oxidation on the entire surface. The thickness of this field oxide film 7 is 5000Å
~8000Å.

(B) Next, through the first mask alignment process, the shielding gate portion 4 of the STI image sensor,
Windows are opened to the control gate portion 6 and source portion 5 at the same time. Next, a polysilicon layer 8 doped with As is formed on the entire surface using a technique such as CVD, and a PSG film 9 is further formed on the entire surface using a CVD technique. As the doping source for the polysilicon layer 8, As is used because it is desired to diffuse the source region 5 as highly and shallowly as possible in consideration of the problem of distortion introduced in the subsequent heat treatment process. The thickness of the polysilicon layer 8 is approximately 3000 Å to 4000 Å.
Å. Also, the thickness of the PSG film 9 is approximately 3000Å~
It is about 4000Å. A CVDSiO ₂ film of the same thickness may be used instead of the PSG film.

(C) Next, by a second mask alignment process, the doped polysilicon layer 8 and PSG film 9 on the region 5 that is to become the source part are left, and the doped polysilicon layer 8 and PSG layer 9 in other parts are removed. Remove completely. Since this step requires dimensional accuracy, it is performed using a dry process such as plasma etching.

(D) Next, boron is diffused or ion-implanted over the entire surface to form p ⁺ diffusion layers 4 and 6 in the shielding gate portion 4 and control gate portion 6. At this time, at the same time as the p ⁺ diffusion layers 4 and 6 are formed in the drive-in diffusion of boron or the heat treatment process after ion implantation, As is diffused from the doped polysilicon layer 8.
A source n ⁺ region 5 is formed. p ⁺ diffusion layer 4,
The impurity density near the surface of the source n+ region 5 is about 1×10 ¹⁹ cm ^-3 cm, and the impurity density of the source n ⁺ region 5 is 1×10 ²⁰
It is about 1×10 ²¹ cm ₋₃ .

In addition, the diffusion depth of the p ⁺ diffusion layers 4 and 6 is approximately 2μ to 5μ.
The diffusion depth of the source diffusion layer 5 is formed accurately with no variation of about 0.5 μm.

(E) Next, after forming a PSG film or CVDSiO ₂ film 9 on the entire surface again to a thickness of about 3000 Å, a third mask alignment process is performed to form a PSG film (or
The CVDSiO ₂ film) 9 and the SiO ₂ film 7 are plasma etched to expose the Si surface above the p ⁺ control gate diffusion region 6.

(F) Next, a Si ₃ N ₄ film 10 is formed on the entire surface using CVD technology. The thickness is approximately 500 Å to 1000 Å.
After the formation of CVDSi ₃ N ₄ film, SnO ₂ or
A transparent electrode 11 such as an ITO (indium oxide/tin oxide) film is formed using a technique such as CVD, and a storage capacitor region of an MIS structure is formed on the control gate 6. Instead of the CVDSi ₃ N ₄ film 10, a thermal Si ₃ N ₄ film or another thermal oxidation film or the like may be formed to a similar thickness. As a method of forming the SnO ₂ transparent electrode 11, as a carrier gas,
CVD technology is used using N ₂ gas and thermal decomposition (400-600°C) of tin tetrachloride (SnCl ₄ ) using antimony pentachloride (SbCl ₅ ) as a doping source.

(G) SnO ₂ in the area above the control gate area
11 and SnO ₂ of the wiring part SnO ₂ leaving 11
After plasma etching the electrode 11, a contact hole to the shielding gate portion 4 is opened (fourth and fifth mask alignment steps). _SnO2
In the plasma etch, CCl ₄ gas was used at 0.1 Torr. Further, an Al electrode is formed on the entire surface by vapor deposition, and the Al is etched, leaving only the Al wiring portion 13 for contact with a predetermined shielding gate 4 and the Al wiring portion for contact with the SnO ₂ electrode 11. Furthermore, after sintering, a final passivation step such as CVD growth of a Si ₃ N ₄ film is performed (sixth and seventh mask alignment steps).

Effects of the Invention As explained above, in the method for manufacturing a solid-state imaging device of the present invention, the positions of the source region 5 and gate regions 4 and 6 of each pixel of the SIT image sensor are simultaneously determined by the first field masking process. , and Figure 4D
Since the gate diffusion regions 4 and 6 and the source diffusion region 5 are formed by the same heat treatment process as shown in FIG. 5 distances are all equalized. Furthermore, the gate diffusion regions 4 and 6 and the diffusion region 5 are formed by the same heat treatment process.
is formed, there is little variation in the gate diffusion depth and source diffusion depth, and in particular, the relative positional relationship in the depth direction between the gate diffusion depth and the source diffusion depth is determined with high precision. Therefore, the relative positional relationship between the gate region and the source region in the surface direction (lateral direction) and the depth direction (vertical direction)
Both the relative positional relationship between the gate region and the source region are formed with high precision and uniformity, and the position and voltage amplification factor of the intrinsic gate point of the SIT forming each pixel are also formed with high precision and uniformity. Therefore, the characteristics of each SIT part can be made uniform, and when viewed as a pixel of an image sensor, the variation in output characteristics with respect to the received light intensity is suppressed to an extremely low level, and fixed pattern noise is reduced.
A large capacity (large number of pixels) image sensor can be realized.

Also, since the source diffusion region uses As,
Shallow diffusion depth of 0.5 μm or less, and 1.0 × 10 ²⁰ ~
Since the structure is optimized to have a high impurity density of 1.0×10 ²¹ cm ^-3 , the diffusion capacitance of the source is small, the resistance of the source region is also small, and an image sensor capable of extremely high speed operation can be realized. Since the upper part of the source region is made of polysilicon, Al
There is no penetration or piping phenomenon of metal into the source region, and despite the shallow source region,
Leakage current etc. are also small and reliability is high.

In addition, the Si surfaces of the gate diffusion regions 4, 6 and source diffusion region 5 of each pixel are on the same plane and are flattened, making it easier to receive light than in conventional manufacturing methods.
The proportion of scattering caused by unevenness on the semiconductor surface has decreased.

[Brief explanation of the drawing]

1A to 1E are diagrams showing a manufacturing process as a conventional example of a gate accumulation type SIT image sensor, and FIGS. 2A and 2B show a manufacturing process as another conventional example of a gate accumulation type SIT image sensor. FIG. 4 is a cross-sectional view of a device structure using the present invention, and is a diagram sequentially showing examples A to G according to the manufacturing process of the present invention. In Figure 4, the SIT of the image sensor matrix part is 1...p ^- substrate, 2...n ⁺ buried layer.
common drain region, 3... high resistance epitaxial layer, channel part of SIT, 4... shielding gate region of split gate SIT, pixel isolation region, 5... source region of split gate SIT,
6... Control gate region of split gate SIT, 7... Field oxide film, 8... As-doped polysilicon layer, 9... PSG film or
CVDSiO ₂ film, 10... Insulating film, 11... Transparent electrode, 12... Al electrode portion, 13... Al contact electrode to shielding gate.

Claims (1)

[Claims] 1 A static induction transistor consisting of an n-type drain region and source region, a p-type control gate region and shielding gate region, and an n-type high-resistance channel region on a p-type Si substrate is defined as one pixel, and the A method for manufacturing a fixed imaging device in which a plurality of pixels are arranged in an X-Y matrix, a first step of forming the drain region on the Si substrate, and forming the channel region above the drain region. The second step is to epitaxially grow high-resistance Si to a thickness of 5 to 10 μm, and a field oxide film of 50 to 8000 μm is grown on the front surface of the high-resistance Si surface.
A third step of forming and a step of simultaneously etching and removing the field oxide film on the high-resistance Si in the portion where the source region, control gate region and shielding gate region are planned to be formed using the first photolithography technique. 4, a polysilicon layer doped with As is formed on the entire surface with a thickness of 3000 to 4000, and then a first PSG or SiO ₂ film is deposited on the entire surface of the polysilicon layer by CVD.
A fifth step of forming the polysilicon layer and the first PSG or SiO ₂ film located above the portion where the source region is to be formed is formed by a fifth step of forming a polysilicon layer of 3000 to 4000 and a second photolithography technique. a sixth step of removing other parts of the polysilicon layer and the first PSG or SiO ₂ film, and removing the control gate region and seal through the exposed window of the high resistance Si in the sixth step; The high-resistance Si on which the ding gate region is planned to be formed
a seventh step of doping boron on the surface of the substrate using the first PSG or SiO ₂ film as a mask;
Through the same heat treatment, the boron is diffused to a depth of approximately 2 μm to 5 μm to form the control gate region and the shielding gate region, and at the same time, the _As is diffused to a depth of 0.5 μm into the high resistance Si. an eighth step of forming the source region; and a second step of forming the source region.
PSG or SiO ₂ film as the field oxide film,
A ninth step of forming the first PSG or SiO ₂ film and the entire upper surface of the exposed window portion of the high-resistance Si, and a third photolithography technique,
the second portion above the control gate region;
Step 10: Etching and removing PSG or SiO ₂ film
and an eleventh step of forming a storage MIS capacitor by forming a gate insulating film over the control gate region and further forming a transparent electrode over the gate insulating film. A method for manufacturing a solid-state imaging device.