JPH0441525B2 - - Google Patents

Description

Detailed Description of the Invention (Technical Field) The present invention relates to an intermediate frequency amplification circuit of a receiver in a mobile radio device, etc., and more particularly to an intermediate frequency amplification circuit having a function of detecting the received electric field strength of the receiver.

(Prior Art) FIG. 1 is a circuit diagram of a conventional intermediate frequency amplification circuit equipped with a reception field strength detection function. This intermediate frequency amplification circuit includes three stages of cascaded amplifiers. The first stage amplifier consists of transistors _Q1 to _Q10 , the second stage amplifier consists of transistors _Q11 to _Q19 , and the third stage amplifier consists of transistors _Q20 to _Q27 . The strength of the input IF signal, that is, the received electric field strength, is determined by connecting the outputs of these stages to capacitors C ₈ ,
It rectified through C ₉ and C ₁₀ , added the rectified voltages of each stage, detected it, and outputted it from terminal 5. However, in this conventional circuit, a high power supply voltage is required to expand the dynamic range of the detected electric field strength by adding voltages. In addition, since it is a voltage addition type, the rectified voltage of each stage is connected to transistors Q ₃₉ , Q ₄₀ , Q ₄₁ ,
Although addition is performed using _Q42 , the linearity of this added portion deteriorates, and as shown in FIG. 2, it is often seen that unevenness appears in the electric field detection voltage. In addition, signal rectification is performed using diodes Q ₂₈ , Q ₂₉ , Q ₃₀ ; Q ₃₂ , Q ₃₃ ,
Since this is done using Q ₃₄ , Q ₃₅ , Q ₃₆ , and Q ₃₇ , the temperature characteristics are particularly poor, and the disadvantage is that the circuit becomes complicated to compensate for the temperature characteristics. Also, each rectifier requires three capacitors C ₈ , C ₉ , and C ₁₀ . The required capacitance of these capacitors increases as the intermediate frequency is lowered. Therefore, these capacitors C ₈ , C ₉ , and C ₁₀ are integrated into ICs because
Generally, the intermediate frequency is 10.7MHz or higher. Lowering the intermediate frequency made it difficult to incorporate a capacitor into an IC, and each stage required a terminal for an external capacitor, making it disadvantageous to use an IC. Furthermore, if the intermediate frequency is increased to 10 MHz or higher, current consumption will increase because the degree of amplification cannot be achieved unless current is passed through the amplifiers in each stage.

(Objective of the Invention) The object of the present invention is to have an input electric field detection function that has excellent linearity and temperature characteristics of the electric field detection voltage, operates at a low power supply voltage, and requires few external parts when integrated into an IC. The present invention provides an intermediate frequency amplification circuit.

(Structure of the Invention) The structure of the present invention is such that the cascade-connected intermediate frequency signals are respectively input signals, and the intensity of the output signal is approximately proportional to the product of the intensity of the input signal and the AGC voltage that is the first DC voltage signal. AGC with n stages (n>1)
an amplifier, a rectifier circuit that rectifies the output signal of the n-th stage AGC amplifier and outputs a second DC voltage signal proportional to the intensity of the output signal; The AGC in the first stage
and an AGC voltage control circuit that generates the first DC voltage signal that is inversely proportional to the nth root of the intensity of the input signal of the amplifier.

(Example) Next, the present invention will be explained in detail with reference to Examples.

FIG. 3 is a circuit diagram of one embodiment of the present invention. This example uses n-stage AGC amplifiers connected in cascade.
A ₁ to _{A o} , rectifier 6, AGC control circuit 7, rectifying capacitor Crec, IF signal input terminals 1 and 1', AGC voltage V _AGC output terminals 2 and 2', and amplified IF It consists of signal output terminals 3 and 3'.

The first stage amplifier A ₁ consists of a current source I ₁ and a transistor
A first differential amplifier having transistors Q ₁₁ and Q ₁₁ ′ and a resistive element R _EI , a second differential amplifier having transistors Q ₁₂ and Q ₁₂ ′, and a transistor Q ₁₃ and
a third differential amplifier with Q ₁₃ ′ and a resistive element R _C1
It consists of. Each amplifier from the second stage to the nth stage
A similar circuit is used for A ₂ to A _o .

The voltage V ₀ (output voltage) of the output IF signal is
is rectified by the rectifying capacitor Crec, and the AGC
The control circuit 7 is configured using a well-known Gilbert multiplier or the like combined with a differential circuit, and each amplifier A ₁
AGC voltage V _AGC is negatively fed back to _Ao , and the output voltage _V0 is controlled to be constant. The AGC control circuit 7 is
The output AGC voltage V _AGC is set so that V _AGC ≦2V _T + R _Ei I _i ...(1). However, V _T is given by the following formula.

V _T =kT/g...(2) Here, k is Boltzmann's constant, T is absolute temperature,
g is the unit charge of an electron.

When the input signal voltage (input voltage) V _IN is V _IN ≦2V _T ...(3), the output voltage V ₀₁ of the first stage amplifier A ₁ is approximately V ₀₁ = R _C1 /2V _T・I ₁ /2V _T +R _E1 I ₁・V _AGC・V _IN ……(4). Also, since the second stage amplifier A ₂ receives this voltage V ₀₁ as input, the output voltage V ₀₂ is V ₀₂ = R _C2 /2V _T・I ₂ /2V _T +R _E2 I ₂・V _AGC・V ₀₁ …… (5) becomes. The amplifiers A ₃ to A _o below operate similarly,
The output voltage V _0i of the i-th stage amplifier is V _0i =K _i ·V _AGC ·V _0(i-1) (6) (K _i is a constant). Therefore, in the i-th stage amplifier, the output voltage V _{0 (i-1) of the previous stage [(i-1) stage] amplifier with respect to the output voltage (output signal strength) V 0i}
The ratio of the product of the AGC voltage V AGC and the AGC voltage V _AGC is a constant value K _i (however, in the first stage amplifier A ₁ , V ₀₀ =V _IN ).

Since each amplifier operates as described above, the relationship between the output voltage V ₀ and the input voltage V _IN is given by the following equation (7). However, let R _L be the resistance component of the load connected between the output terminals 3 and 3'.

V ₀ = R _C1 /2V _T・I ₁ /2V _T +R _EI I ₁・V _AGC ×……×R _L R _Co /2V _T (R _Co +R _L ) ・I _o /2V _T +R _Eo I _o・V _AGC・V _IN = R _CI ×……×R _Co / (2V _T ) ⁿ・R _L / (R _Co + R _L )・I ₁ ×……×I _o / (2V _T + R _E1 I ₁ ) ×…… ×(2V _T +R _Eo
I _o ) ・(V _AGC ) ⁿ・V _IN ……(7) Calculating V _AGC from this equation (7), becomes.

In this way, the AGC voltage V _AGC is the input voltage V _IN
It is a value proportional to 1/ ⁿ √ _IN when , and is expressed by compressing V _IN . Therefore, it can be seen that the dynamic range of V _AGC is compressed to 1/n in dB value with respect to the dynamic range of input voltage V _IN . Now, the dynamic range of input voltage V _IN and
If the product of the dB value and the compression ratio 1/n is about 20 dB, the dynamic range of V _AGC will change by at most one order of magnitude. Therefore, in that case, it can be considered that almost pseudo-logarithmic compression characteristics can be obtained. Now, if the dynamic range of the input voltage V _IN in this embodiment is 60 dB, then the dynamic range of V _AGC will be 20 dB if n=3, which will change by only one order of magnitude.

FIG. 4 is a diagram showing the relationship between the input voltage V _IN and the AGC voltage V _AGCO in the embodiment shown in FIG. In this diagram, V _IN
= 0dB, V _AGC V _AGCO , V _IN from 0dB
V _AGC /V _AGCO when it changes up to 60 dB is shown using the number of amplifier stages n as a parameter. As can be seen from this figure, input voltage V _IV can be detected by AGC voltage V _AGC , and input voltage V _IN and AGC voltage
V _AGC is obtained from a relationship with almost pseudo-logarithmic characteristics.

(Effects of the Invention) As described in detail above, the intermediate frequency amplifier circuit of the present invention is configured with an AGC circuit consisting of multi-stage AGC amplifiers, and the AGC voltage when the final stage output voltage V ₀ of the AGC circuit is constant. This method uses V _AGC to detect the input electric field level V _IN of the intermediate frequency amplifier circuit. This intermediate frequency amplification circuit requires only one rectifier, and therefore only one rectifier capacitor. Even if the intermediate frequency is too low to incorporate a built-in capacitor, it can be handled by simply adding one terminal for an external capacitor. Therefore, by attaching only one external capacitor, the necessary gain can be obtained even if the value of current flowing through the AGC amplifiers in each stage is reduced by lowering the intermediate frequency, thereby making it possible to reduce current consumption. Further, since addition of rectified voltages is not performed, the electric field detection voltage is also almost logarithmically compressed and becomes a monotonous curve. Further, since the temperature characteristic of the electric field detection voltage is also monotonic, temperature compensation can be easily performed.
Additionally, this method has many advantages, as it allows for lower voltages, and the circuit can be realized with a power supply voltage as low as 2V.

In summary, according to the present invention, the linearity of the electric field detection voltage and temperature characteristics are excellent, the operation is performed at a low power supply voltage, and the number of external components required when integrated into an IC is small.
An intermediate frequency amplification circuit having an input electric field detection function can be provided.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional intermediate frequency amplification circuit, Figure 2 is a characteristic diagram of this conventional circuit, Figure 3 is a circuit diagram of an embodiment of the present invention, and Figure 4 is a characteristic diagram of this embodiment. be. 1, 1'...Intermediate frequency signal input terminal, 2, 2'...
...AGC voltage output terminal, 3, 3'... Output terminal of amplified intermediate frequency signal, 5... Field strength detection voltage output terminal, 6... Rectifier, 7... AGC control circuit,
_A1 ~ _Ao ...AGC amplifier, _I1 ~ _Io ...constant current source.

Claims (1)

[Claims] 1. n stages (n >1); a rectifier circuit that rectifies the output signal of the n-th stage AGC amplifier and outputs a second DC voltage signal proportional to the intensity of the output signal; and the second DC voltage. input the signal and generate the first DC voltage signal that is inversely proportional to the nth root of the intensity of the input signal of the first stage AGC amplifier.
An intermediate frequency amplification circuit comprising an AGC voltage control circuit.