JPH0441538B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a pilot signal erasing circuit for erasing a 19 KHz stereo pilot signal contained in a stereo composite signal.

(B) Prior art A stereo composite signal consists of a stereo sum signal (L+R), an amplitude modulated stereo difference signal (L-
R) and a stereo pilot signal P. Therefore, the stereo sum signal and the stereo difference signal are processed in the stereo decoder.
Demodulation is performed based on a 38KHz signal synchronized with the stereo pilot signal, and a left stereo signal L and a right stereo signal R are obtained. In this case, it is desirable that the demodulated signal does not contain a stereo pilot signal, and conventionally a pilot signal canceling circuit has been provided at the input end of the stereo decoder. 1st
The figure shows a stereo demodulation circuit equipped with the conventional pilot signal canceling circuit, in which 1 is an input terminal to which a stereo composite signal is applied, and 2 is an input terminal that is synchronized with the stereo pilot signal included in the stereo composite signal. 19KHz signal and 38K
3 is a level detection circuit that detects the level of the stereo composite signal in the stereo composite signal using the 19KHz signal obtained from the PLL circuit 2; 4 is the level detection circuit of the level detection circuit 3; A level modulation circuit modulates the level of the 19KHz signal obtained from the PLL circuit 2 according to the output signal, 5 a waveform shaping circuit that shapes the waveform of the output signal of the level modulation circuit 4, and 6 the stereo composite signal. a subtraction circuit that subtracts the stereo pilot signal contained therein and the level-controlled 19KHz signal obtained from the waveform shaping circuit 5 to erase the stereo pilot signal;
and 7 are stereo decoders that generate left and right stereo signals using the output signal of the subtraction circuit 6 and the 38 KHz signal that is the output signal of the PLL circuit 2. The PLL circuit 2 internally includes a phase comparator, a low-pass filter, a voltage-controlled oscillator, a frequency divider, etc., and generates a signal synchronized with the stereo pilot signal, but since it is well known, the details are omitted. do. The level detection circuit 3 is constituted by, for example, a synchronous detection circuit, and generates a DC signal corresponding to the level of the stereo pilot signal at its output terminal. The level modulation circuit 4 uses the DC signal to
The level of the 19KHz signal generated from the PLL circuit 2 is changed, and a level-adjusted 19KHz signal is generated at the output end. The waveform shaping circuit 5 is
19KHz obtained at the output end of the level modulation circuit 4
This is for converting a rectangular wave signal to a 19KHz sine wave signal, and is composed of an LC parallel resonant circuit. The subtraction circuit 6 is arranged to subtract the stereo composite signal and the 19KHz sine wave signal and erase the stereo composite signal.
As a result, a stereo composite signal without a stereo pilot signal is applied to the stereo decoder 7.

The pilot signal cancellation circuit shown in Fig. 1 has the advantage of having a higher cancellation effect compared to the case where the stereo pilot signal is canceled using simply a level-modulated 19KHz rectangular wave signal, but on the other hand, it uses an LC parallel resonant circuit as a waveform shaping circuit. This has the disadvantage that the erasing effect deteriorates due to phase changes and characteristic changes due to element variations and changes in temperature characteristics.
Since it requires a coil L and a capacitor C that cannot be integrated into an IC (integrated circuit), it has the disadvantage of being unsuitable for integration into an IC (integrated circuit).

(c) Purpose of the Invention The present invention has been made in view of the above points, and provides a method that has a high erasing effect on stereo composite signals and
The present invention aims to provide a pilot signal erasing circuit that can be easily integrated into an IC.

(D) Structure of the Invention The pilot signal erasing circuit according to the present invention comprises: a PLL circuit that generates a first signal synchronized with a stereo pilot signal included in a stereo composite signal and a harmonic signal of the first signal; A level detection circuit detects the level of the stereo composite signal, and according to the output signal of the level detection circuit,
a plurality of level modulation circuits that modulate the levels of the first signal and its harmonic signals; a level ratio setting circuit for setting the levels of the output signals of the level modulation circuits in a predetermined relationship; and the level ratio setting circuit. and an arithmetic circuit that adds or subtracts the output signal of the synthesis circuit and the stereo composite signal.

(E) Embodiment FIG. 2 is a circuit diagram showing an embodiment of the present invention.
is the 19KHz included in the stereo composite signal
A PLL circuit 91 generates a 19KHz rectangular wave signal (first signal) synchronized with the stereo pilot signal, a 38KHz rectangular wave signal, and an odd harmonic signal of the first signal, and ₉₁ uses the output signal of the level detection circuit 3. hand,
A first level modulation circuit ₉₂ that performs level modulation of the first signal is similarly obtained from the PLL circuit 8.
A second level modulation circuit 9n that performs level modulation of a 57KHz square wave signal (third harmonic of the first signal) is a (19×n)KHz signal obtained from the PLL circuit 8.
(However, n is an odd number) Rectangular wave signal (nth signal of the first signal)
10 ₁ is a first level ratio setting circuit that outputs the output signal of the first level modulation circuit 9 ₁ as “level 1”; 10 ₂ is the second level A second level ratio setting circuit that outputs the output signal of the modulation circuit 9 ₂ as "level 1/3", 10n is the n-th level modulation circuit 9n
An n-th level ratio setting circuit outputs the output signal as "level 1/n", and a synthesizing circuit 11 synthesizes the output signals of the first to n-th level ratio setting circuits ₁₀₁ to 10n. Note that the parts in FIG. 2 that are common to FIG.

The first signal synchronized with the stereo pilot signal obtained at the output end of the PLL circuit 8 and its harmonic signals are transmitted to the first to nth level modulation circuits _{9 1} respectively.
In steps 9n to 9n, the level is modulated by a signal corresponding to the level of the stereo pilot signal obtained from the level detection circuit 3. Therefore, the output signal levels of the first to n-th level modulation circuits ₉₁ to 9n are proportional to the level of the stereo pilot signal in the composite signal. By the way, the first signal is a 19KHz rectangular wave signal, which includes odd harmonic components. It is known that the level of the harmonic component is 1/n of the fundamental wave of 19 KHz (where n is the order of the harmonic signal). For example, the level of the third harmonic component of 50 KHz is 1/3, and the level of the fifth harmonic component of 95 KHz is 1/5. However, if the output signal of the first level modulation circuit ₉₁ is directly used as an erasure signal, the odd-order harmonic components will remain in the stereo composite signal, which is inconvenient.

The level-controlled 19KHz rectangular wave signal, which is the output signal of the first level modulation circuit 9 ₁ , is applied to the first level ratio setting circuit 10 ₁ and outputted from the first level ratio setting circuit 10 ₁ to “level 1”. is output as a signal. Further, the level-controlled 57KHz rectangular wave signal, which is the output signal of the second level modulation circuit 9 ₂ , is applied to the second level ratio setting circuit 10 ₂ , and from the second level ratio setting circuit 10 ₂ . Output as a level 1/3" signal. Similarly, the nth
The level ratio setting circuit 10n generates a (19×n) KHz rectangular wave signal of “level 1/n”.

The synthesis circuit 11 synthesizes the output signals of the first to n-th level ratio setting circuits 10 ₁ to 10n. Therefore, the third harmonic component of "level 1/3" in the first signal applied from the first level ratio setting circuit 10 ₁ and the "level 1/3" component applied from the second level ratio setting circuit 10 ₂ are combined. Similarly, the n-th harmonic component of "level 1/n" in the first signal and the "level 1/n" 57KHz rectangular wave signal applied from the n-th level ratio setting circuit 10n are canceled. n'' (19×n) KHz square wave signal is canceled,
As a result, only the 19KHz component of the first signal is generated at the output terminal of the synthesis circuit 11. Therefore, if the output signal of the synthesis circuit 11 is adjusted by the volume and applied to the subtraction circuit 6, a stereo composite signal from which the stereo pilot signal has been removed is obtained at the output terminal of the subtraction circuit 6.

As mentioned above, the level of the harmonic components contained in the first signal becomes smaller as the order becomes higher. Therefore, the pilot signal canceling circuit shown in FIG. 2 is effective as long as it is able to cancel at least the third harmonic component (57 KHz) in the first signal. Naturally, the greater the number of canceled harmonic components, the greater the effect. In the embodiment, the subtraction circuit 6 is used to erase the stereo pilot signal from the stereo composite signal, but an addition circuit may be used in consideration of the polarity of the output signal of the synthesis circuit 11. is also possible.

FIG. 3 shows an example of a level modulation circuit, in which a DC signal corresponding to the stereo composite signal level is sent to the first input terminal 12, and the DC signal is sent to the second input terminal 13.
A level-modulated signal (the first signal and its harmonic signal) is applied to each of the input terminals, the transistor 14 is switched by the level-modulated signal, and a modulated output is generated at the output terminal 15. Also,
Figure 4 shows another example of the level modulation circuit.
A DC signal corresponding to the stereo pilot signal level is applied to the first input terminal 16, and a level modulated signal is applied to the second input terminal 17. Level modulation is performed using an input transistor 20 connected to. Figure 5 shows
This shows an example of a level ratio setting circuit.
1, a resistor 22 and a variable resistor 23 that constitute a feedback path from its output end to its negative input end. The output signal of the level modulation circuit applied to the input terminal 24 is amplified with a gain determined by the adjustment of the variable resistor 23, and is generated at the output terminal. Therefore, by adjusting the value of the variable resistor 23 and applying it to the first signal and its harmonic signals, output signals having a level ratio having a predetermined relationship can be obtained.

(f) Effects of the Invention As described above, the present invention has the advantage of providing a pilot signal erasing circuit that can reliably erase the stereo pilot signal contained in a stereo composite signal. Furthermore, according to the present invention, there is no need for a waveform shaping circuit consisting of a coil or capacitor that cannot be integrated into an IC.
This has the advantage that it is easy to process and does not cause changes in characteristics.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional pilot signal erasing circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention, Fig. 3 is a circuit diagram showing an example of the level modulation circuit, and Fig. 4 is a circuit diagram showing an example of the level modulation circuit. FIG. 5 is a circuit diagram showing another example thereof, and FIG. 5 is a circuit diagram showing an example of the level ratio setting circuit of FIG. 2. Explanation of main drawing numbers, 3...Level detection circuit, 6...
...Subtraction circuit, 8...PLL circuit, 9 ₁ , 9 ₂ , 9n...
... Level modulation circuit, 10 ₁ , 10 ₂ , 10n ... Level ratio setting circuit, 11 ... Synthesis circuit.

Claims (1)

[Claims] 1 A circuit for erasing a stereo pilot signal included in a stereo composite signal, the first circuit being synchronized with the stereo pilot signal.
generating a signal and a harmonic signal of the first signal.
A PLL circuit, a level detection circuit for detecting the level of the stereo pilot signal, and an output signal of the level detection circuit are used to perform level modulation of the first signal and a harmonic signal of the first signal. A plurality of level modulation circuits that generate signals corresponding to the level of a stereo pilot signal, a level ratio setting circuit that sets the levels of output signals of the plurality of level modulation circuits in a predetermined relationship with each other, and the level ratio setting circuit. The stereo composite signal is composed of a synthesis circuit that synthesizes the output signals of the synthesis circuit, and an arithmetic circuit that adds or subtracts the output signal of the synthesis circuit and the stereo composite signal. A pilot signal erasing circuit designed to obtain a pilot signal.