JPH0441834B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a screen superimposition device that superimposes a plurality of screen signals stored in a plurality of screen memories by setting priorities.

Prior Art and its Problems Conventionally, in order to display superimposed screens on a display device such as a CRT display device, a screen superimposition device has been used in the previous stage.

Figure 1 is a conceptual diagram to explain the principle of superimposing screens. Screen A consists of a red (R) circle drawn in a transparent (T) background, and When overlapping screen B consisting of a rectangular blue color (B), if you simply overlap the two, the overlapping portion of R and B will become magenta (M) due to additive color mixing, as shown in Figure C'. becomes. However, in cases where screen A is a portrait of a person and screen B is a distant view that should serve as the background, it may be desirable to give priority to screen A and superimpose the images, as shown in FIG.

FIG. 2 is a block diagram of a conventional device for performing the above-mentioned preferential superimposition, illustrating a case where three screens are superimposed. 1 to 3 are screen memories that store each of the three screens to be superimposed; 11 to 13 are bus drivers; 14 to 16
1 is a data bus, 17 is a bus selector, 18 is a priority determination circuit, and 20 is a data bus connected to a video signal generation circuit. Screen signals outputted from the screen memories 1 to 3 to the corresponding data buses 14 to 16 via the corresponding bus drivers 11 to 13 are coupled to a bus selector 17 and a priority determination circuit 18. The priority determination circuit 18 selects a data bus to be connected to the data bus 20 according to the priority of the screen signal on each data bus and whether or not the screen signal is transparent.
The bus selection signal is sent to the bus selector 1 via the signal line 19.
Output to 7. Assuming that screen signals are prioritized in the order of screen memories 1, 2, and 3,
The priority determination circuit 18 selects data buses 14 to 16 according to the following rules. When the output of the screen memory 1 is not transparent, the data bus 14 is unconditionally selected. When the output of the screen memory 1 is transparent and the output of the screen memory 2 is not transparent, the data bus 15 is selected.
Data bus 16 is selected only if the outputs of and 2 are transparent.

In the conventional example described above, a data bus corresponding to the number of screen memories is required, resulting in a problem that the data bus portion becomes complicated and expensive. This causes problems in that the number of screens that can be superimposed and the number of display colors (the number of signal lines per data bus) are limited.

OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a screen superimposition device in which the data bus portion is simplified and the cost is reduced.

Summary of the Invention The present invention, which achieves the above object, provides a priority level setting register and a priority level comparison circuit for each screen memory, and outputs a non-transparent highest priority level on a data bus connecting all screen memories and a priority level. It is configured to superimpose screens by outputting screen memory data and priorities.

Hereinafter, the present invention will be explained in further detail with reference to Examples.

Embodiment of the Invention FIG. 3 is a block diagram of an embodiment of the present invention, and 1 to 3 are screen memories. In this embodiment, since the internal configuration of each screen memory is the same, only the internal configuration of the screen memory 1 is illustrated.

In the screen memory 1, 4 is a screen memory plane, 5 is a priority level setting register, 6 is a data bus driver, 7 is a priority level driver, 8 is a priority level comparison circuit, 9 is a priority level bus, and 10 is a data bus. .

In this configuration, in order to display a superimposed screen on the CRT monitor device, the screen memory plane 4 is generated by a video signal generation circuit (not shown).
Suppose that is read out. At this time, screen memory 2 and 3
The internal screen memory plane (not shown) is also read out at the same time. On the other hand, a priority level is externally set in a priority level setting register (priority level setting register 5 in the screen memory 1) in each screen memory by a special code. This code is input to the priority level comparison circuit in each screen memory (priority level comparison circuit in screen memory 1}) and the open collector (or drain) priority level bus driver (priority level bus driver 7 in screen memory 1). ) and drives the priority level bus 9 that overlaps all the screen memories 1 to 3. The priority level comparison circuit in each screen memory compares the setting code set in the corresponding priority level setting register with the code on the priority level bus 9, and determines that its own priority level is the priority level on the priority level bus 9. When the level is lower than the level, output of own priority level and read data to the bus driver is prohibited.

Therefore, after a certain period of time has elapsed since all the screen memories simultaneously output their respective priority level codes to the priority level bus 9 (after reaching a steady state), the read data is transparently transmitted to the priority level bus 9. The priority level code of the highest priority level among the screen memories that are not used is outputted, and the read data of the corresponding screen memory is outputted to the data bus 10.

This output data is priority superimposed data and is sent to a video signal generation circuit (not shown).

FIG. 4 is a block diagram showing an embodiment of the screen memory 1 shown in FIG. 3 together with peripheral circuits.

In this embodiment, the priority level bus 9 consists of four signal lines 91 to 94, and is configured so that up to eight screens can be superimposed.

Each of the bits P0 to P3 in the priority level determination register 5 is externally set with an inverted priority level code according to the priority level previously assigned to each screen memory. 81 is a comparison circuit which compares its own priority level code set in the priority level setting register 5 and the priority level code on the priority level bus 9, and if its own priority level is lower, A>B. A high level (H) is output to the output terminal 82 to inhibit the output of the bus driver. R, G, B, and BL are data read from the screen memory 4, and are bits corresponding to red, green, blue, and blink, respectively. 84 is a logic gate that detects that the read data is transparent (R, G, and B are all L). Data bus driver 6 and priority level bus driver 7
Each logic gate within has an open collector or open drain configuration. 85 is an inverter, which is a logic gate for converting the priority level code (negative logic) on the priority level bus 9 to positive logic.

Under such a configuration, it is assumed that a code obtained by inverting the priority level code as illustrated in FIG. 5 is externally set in the priority level setting register 5. The signal lines 91 to 93 of the priority level bus 9 are all at high level (H) because they are pulled up by a group of pull-up resistors (not shown).
It is the lowest priority level. Therefore, a low level (L) is output to the output terminal 82 of the comparison circuit 81. In this case, if the read data from the screen memory plane 4 is not transparent and the output of the logic gate 84 is low, the output of the NOR gate 83 among all the logic gate 2 inputs in the data bus driver 6 and the priority level bus driver 7 All inputs connected to the terminal become high, and the read data from the screen memory plane 4 and the priority level code from the priority level setting register 5 are output to the corresponding buses.

Priority level codes are similarly output from other screen memories to the priority level bus 9, but the comparison circuit in each screen memory (comparison circuit 81 in screen memory 1) always writes the priority level code to its own priority level setting register. The set priority level code and the priority level on the priority level bus 9 are compared, and if a higher priority level than the self is output on the priority level bus 9, the own priority level code and the screen memory are output. Prohibits output of read data from the plane to the corresponding bus. Therefore, after a certain period of time after each screen memory outputs the priority level code and read data onto the priority level bus 9 and data bus 10, only the priority level and read data of the screen memory with the highest priority level will be on the bus. It will be output. The read data on the data bus 10 is supplied to a video signal generation circuit (not shown) as a complete superimposed screen.

Note that when the read data from the own screen memory plane is transparent, the logic gates 84,
83 and 86 prohibit low output to the bus regardless of the priority level. Also, among the logic gates in the priority level bus driver 7, only the one related to the priority level P0 has a different configuration from other logic gates, but this is due to the racing (flapping) of data on the priority level bus 9. This is to prevent For example, suppose that two screen memories whose priority level codes are "LHHH" and "HLLL" are superimposed, and the priority level codes from each of the screen memories are simultaneously output onto the priority level bus 9. . On the priority level bus 9, a logical sum of negative logic is taken for each bit, so the logical sum of the above-mentioned "LHHH" and "HLLL" becomes "LLLL" (highest priority level).
As a result, output from not only the low priority level "HLLL" screen memory but also the high priority level "LHHH" screen memory is prohibited, and the output on the priority level bus 9 is again "HHHH" (lowest priority). level), and each screen memory outputs its own priority level code onto the priority level bus 9 again. There is a problem in that such operations are repeated continuously, and the data on the priority level bus 9 is not stable even after a certain period of time has elapsed. Such a problem can be avoided by making the output condition on the bus of P0, which is the MSB of the priority level code, irrelevant to the output condition of the comparison circuit 81, as shown in FIG.

FIGS. 6 to 8 illustrate the correspondence between screen memory and priority level codes in cases where there are three to one priority level buses 9, respectively. The priority level code in the figure is the level on the priority level bus 9, and the setting code in the priority level setting register 5 is the inverse of these.

Effects of the Invention As explained above, the present invention provides a priority level setting register and a priority level comparison circuit for each screen memory, and provides the highest priority level with no transparent output on the data bus and priority level bus connecting all the screen memories. Since the screen is configured to be superimposed by outputting the data and priority of the screen memory of each screen, there is an advantage that the configuration of the data bus can be made simple and inexpensive.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram explaining the preferential overlapping of screens, FIG. 2 is a block diagram of a conventional device, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a screen shown in FIG. 5 to 8 are conceptual diagrams for explaining the operation of the present invention. 1 to 3...Screen memory, 4...Screen memory plane, 5...Priority level setting register, 6...Data bus driver, 7...Priority level bus driver, 8...
Comparison circuit, 9...priority level bus, 10...data bus.

Claims (1)

[Scope of Claims] 1. A screen superimposition device that superimposes a plurality of read data stored in a plurality of screen memories with priorities set, comprising a data bus and a priority level bus connecting each screen memory, and The screen memory includes a priority level setting means for setting its own priority, a means for determining whether or not its own read data is transparent, and a means for determining whether or not the read data of the screen memory is transparent, and the contents of the priority level setting means and the contents on the priority level bus. and a comparison means for comparing the own read data and the own priority on the data bus and the own priority level, respectively, when the own read data is not transparent and the own priority is higher than the priority on the priority level bus. If the own read data is transparent or the own priority is lower than the priority on the priority level bus, the own read data and the own priority are output to the data bus respectively. and means for prohibiting output onto a priority level bus.