JPH0442320A - File data transfer device - Google Patents

Abstract

PURPOSE:To reduce the load on a main CPU and to improve the hard disk HDD access performance by providing a file accelerator between the HOST side and an HDD. CONSTITUTION:A file accelerator 5 consists of a CPU 51, a direct memory access controller DMAC 7, a bus controller 8, a register group 9 equivalent to the control register group contained in an HDD 6, and a register group 10. The accelerator 5 is positioned between the HOST side where a main CPU 1, a main memory 2, etc., are included and the HDD 6. As a result, the load on the CPU 1 is reduced and at the same time the access performance of the HDD 6 is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method and apparatus for transferring file data in a personal computer, workstation, etc.

[Conventional technology]

Conventional ISA (Industry 5tanda)
rd Architecture) - A personal computer with an AT Babasu.

In workstations and the like, a main CPU on a personal computer, workstation, etc. performs data transfer processing when reading data from a hard disk or writing data to a hard disk. For example, IBffiPC/AT Technic
al Reference, HDDDRR04 for AT
Please refer to the 0C product specifications.

As an example, the system configuration of a personal computer equipped with a hard disk is shown in FIG.

A hard disk (HDD) 46 used in the personal computer 40 in the figure is an AT HDDDRRO 40.
As described in item 15 of the Cm product specifications, in addition to the data bus, chip select signals (C8O, C3l), address (Ao-A2), read timing control signal (IOR), write timing (IO
There is W).

Therefore, in this configuration, in order to connect the personal computer 40 and the HDD 46, a system configuration in which an HDD adapter 47 is added which has an address decoder 471 that only decodes the address and generates the HDD CS○ and C81 signals is added. It becomes.

In this configuration, the main CPU 41
When writing data for multiple sectors by 1 (/),
The main CPU 41 first calculates a physical address for the HDD 46 from the logical address of data from the operating system, sends a command with the physical address added to the HDD 46, and waits for the HDD 46 to complete preparations for data transfer.

After that, the main CPU 41 indicates the completion of data transfer by H.
When detected by the interrupt signal (IRQ) from DD46,
To implant 1 - String instruction (EnputStrin)
g In5truction) or Output String In5tr
uction), and the main memory 4l- is executed.
Data is transferred between HDDs 46. When the data transfer of one sector is completed, an interrupt is generated from the HDD 46 every time, and the main CPU 41 performs the interrupt processing and then executes the data transfer of the next sector again. The above process was repeated for the specified number of sectors.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into consideration the burden on the main CPU when reading/writing multiple sectors to/from the HDD, and has a higher priority than HDD processing.
If I10 processing such as communication occurs at the same time, the main CPU's processing for the HDD is interrupted. When restarting, the restart of data transfer with the HDD was delayed by up to 16.7 m5ec due to waiting for the HDD to rotate, and the performance when accessing the I-I D of the personal computer deteriorated to less than half. There was a problem with it.

The object of the present invention is to provide the above-mentioned conventional personal computer,
The object of the present invention is to prevent performance deterioration when accessing the HDD of the personal computer, workstation, etc. in a system using an HDD used in a workstation or the like. A further object of the present invention is to reduce the processing load on the main CPU and to improve the performance of a personal computer.

The purpose of this system is to provide a system in which the main CPU can execute other ■/○ processes even when a workstation is accessing the HDD.

[Means for Solving the Problems] In order to achieve the above object, in the present invention, a file accelerator is provided, and the load on the main C and PU is reduced within the file accelerator, and
A CPU that realizes the disk cache function, and Direct Me that allows high-speed data transfer between the HDD and main memory to prevent performance deterioration when accessing the HDD.
mory Access Control-11er (D
MAC), bus control means for controlling the bus at that time, and at least a register group equivalent to the control register group in the HDD.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 3.

The file accelerator 5 of the present invention, as shown in FIG.
It is located between the main memory 2 and the HDD 6, and controls information transfer such as command status between the two and data transfer between the main memory 2 and the HDDB.

FIG. 1 shows an example of the internal configuration of the file accelerator 5. As shown in FIG. In this embodiment, the file accelerator 5 is a CPU 51. Direct memory access
Controller (DMAC) 7° bus controller 8. H
Register group equivalent to control register group in DD9. It consists of a register group 10.

In the figure, the CPU 51 realizes a disk cache function by using information in the register group 10 and the buffer memory in the HDDe, and responds to an interrupt signal IRQ2 from the HDD 6 that is generated every time one sector is read or written. interrupt processing is executed, and the final result after command execution is set in the status register of register group 9. This reduces the load on the main CPU, and at the same time improves I-IDD access performance by realizing a disk cache function.

In addition, the DMAC 7 allows data transfer between the HDD 6 and the main memory 2 to be performed at a higher speed than the reading or writing speed in the HDD e without interruption.
It is possible to prevent the HDD 6 from having to wait for rotation during the data transfer. Thereby, HDD access performance deterioration can be prevented.

Also, register group 9 (R, N000~9) is the main C
Can be read from PUI, and file accelerator 5
The contents of each register are as shown in FIG. Also, register group 10 (R
, No., O-9) can be read from the main CPU 1 and read from the CPU 51, and the contents of each register are as shown in FIG. In this embodiment, the register group 9 and the register group 10 have the same contents as the register group inside the HDD 51.

Furthermore, as shown in FIG. 3, the bus controller 8 controls data bus switching and transfer when information is transferred from the main CPUI to the register group 10 and internal registers other than the command register in the HDDG. Signals AO, At, A2. C8O.

Outputs C8I, l0WD, WEB, RC8O to RC, S9, and sends information from the main CPUI to register group 10 and H
Write simultaneously to the internal registers of DD6. As a result, in the file transfer system using the file accelerator 5 of this embodiment, H
Information can be quickly transferred to the DD6.

Also, when transferring information from register group 9 to main CPUI, data bus switching and transfer control signals RDA and C8A
Output O-C8A9.

Furthermore, when the CPU 51 performs a read/write operation on the register groups 9 and 10, the bus controller 8 connects the data bus B and the data bus A, and transmits the transfer control signal C8A.
O-CSA9. ! :Outputs RDB (when reading L/DI, 1st group 10) or WEA (when reading register group 9, I~).

Further, when the CPU 51 accesses the internal register of the HDD 6, the bus controller 8 connects the data bus B and the data bus, and sends AO to A2. as transfer control signals. C
8O, C8I l0WD (when writing) or l0RD
(when reading) is output.

As a result, the CPU 51 writes the contents of the command register (R, No., 7) of the register group 10 to the equivalent register in the HDDB, reads the contents from the register equivalent to the register group 9 in the HDDe, and writes the contents to the register group 9. Can be set.

Now, in FIG. 2, when the main CPU 1 causes the HDD 6 to perform a write operation, the main CPU 1 sends write pre-competition information (Write
Precomp Information), Sector Count indicating the amount of data
), a sector indicating the location of the first data on the disk.
Number (Sector Number) Cylinder Low (Cylinder Low) Cylinder High (Cyl
inter High), drive/head (Dri
By outputting command parameter information such as ve/Head) address on the address via the data bus and outputting the IOW signal, the information is transferred to the register group IO in the file accelerator 5 shown in FIG. Write.

However, by this time, the CPU 51 has outputted the control signal CPUB/HO8T of the selector 11 shown in FIG. It is assumed that the word HO8T/REG is output to connect the data bus B to the data A, and the multiplexer 13 and the data bus are set in a disconnected state.

When the command parameter information is written to the register group 10, the bus controller 8 outputs C3A0 to C3A9 from the decoder 12 and also outputs WEB to the register group 10. At the same time, the address AO-A2 of the lower 3 bits of the address from the main CPU 1 is sent to the HDD 6 via the selector 11 for games 1 to 15 to 16.
output from the decoder 12 and game I~18
D6 internal register chip select signal C8O,C
8I signal is output, and the IOW from the main CPUI is 1-19. It is output to l0WD via gate 20.

Therefore, the command parameter information is written to the register group 10 via the data bus, and at the same time the command parameter information is written to the HDDS.
is written to an internal register within the

Next, the main CPUI outputs the specified address and writes the write sector (as in the case of command parameter information).
Write 5ectors) command to register group l
Write to the command register in O.

At this time, the decoder 12 outputs a command (Command
) A register selection signal is output to gates 1 to 14 and gate 22, the output of gate 22 masks the ■○WD signal for HDD 6, and gate 14 outputs an activation signal IRQI to CPU 51.

When the CPU 51 detects the activation signal, it performs the following processing.

The CPUB/HOST signal is changed so that the input to the decoder 12 is the address bus B from the CPU 51, and then the contents of each register in the register group 10 are read.

Next, the contents of the command register in register group 10 are set to write to the disk in sectors 1 to υri.
After confirming that it is a teSectors) instruction, select H
Change the O8T/REG signal to connect data bus B to the data bus. After that, the write sector (Wri)
te 5ectors) command is written to the HDD 6 via the data bus.

At this time, bypass capacitors 1 to rollers 8 send gate 1 to HDD 6 based on the address, WE, etc. input from CPU 23.
From 5 to 16, address AO-A2 to game 1 18,
C8O, 'C, S1 from decoder 12, game 1-20
A control signal such as 10WD is output from the terminal. The core, HO
Change 8T/REG and disconnect data bus B and data bus.

The sector number (Sect-o) of the command parameter
r Number), sector 0 count (Cecto
Calculate the number of data that can be transferred from
DC8, W
It is set in DMAC7 by the transfer control signal E.

Next, when it detects that the transfer request interrupt signal IRQ2 from the HDD 6 is active, it outputs a transfer activation signal DREQ to the DMAC 7.

As a result, the DMAC7 outputs HREQ indicating a data bus use request to the main CPUI, and after confirming that the response signal HACK has become active, the DMAC7 outputs the address to the main memory and the memory read timing DMRD.
Outputs DWR, DACK and transfers HD from main memory 2.
Start data transfer to D6. At this time, as shown in FIG. 7, the bus controller 8 outputs ■○WD in response to the DWR signal from the DMAC 7, and outputs C8O and the fixed address AO-A2 in response to the DACK signal.

The above data transfer is repeated until the transfer of one sector of data is completed. However, the main CPU
When accessing the Read Data register or the Write Data register, if the decoder 12 of the bypass capacitor 1 and roller 8 does not output the RCO signal, the main The CPUI reads the read data in the HDD6.
Date) register or write data (Write) register.
e Date) register can be accessed.

After this, the I-I D D 6 issues a 1-sector transfer end interrupt from the i RQ 2, so when the CPU 51 detects this, it reads the status in the HD D S via the bus controller 8 and responds to the status. Execute interrupt processing. If it is normal, the CPU 51 returns to D.
The MAC 7 is activated, data transfer is resumed, and the same process as above is repeatedly executed. The CPU 51 performs the above processing in a specified sector from the main CPU
After repeating execution for several minutes to Callan 1, the re-termination result for the command from the main CPUI is sent to the status register (CR1No, 9) of register group 9 and the alternate
The status is set in the Alternate status register (R, NO, 8), a command end interrupt is issued to the main CPU by the iRQ signal, and the processing of the CPU 51 ends.

However, since one sector of data is transferred by the DMAC 7 shown in FIG. 7 above within the rotation time of one sector of the HDD 6, a rotational wait time occurs during the write operation of the I-IDD 6. Since the bus cycle of the main CPtJ1 is also secured, the main CPU1 is connected to the HDD mentioned above.
6, other ■/ such as communication etc.
○ Processing can also be executed.

Next, when the main CPUI performs a read operation on the HDD 6, the direction of data transfer is only from the HDD 6 to the main memory 2, and the processing of the file accelerator 5 is basically almost the same as during the write operation. There is, but only file accelerator 5 is the main CPU
Read selectors from I (Read 5ectors
) When the CPU 51 receives the instruction, the CPU 51 register group 1
0's command para two 1 pa.

Evening Information Sector Count
+Sector Number
y Cylinder Lotu z
Cylinderlligh +
Drive/Head and cpU
If the information managed by the CPU 51 itself detects that the data remaining in the data buffer in the HDDS is the data requested by the main CPU, the disk cache is filled up to 1 or more, and the CPU 51 H.
Read 13uf for DD6
fer) command, and if there is no error, issue the read sector (Read 5ectors) command H.
Issued to DD6.

The subsequent data transfer process is the same as from 541 onward. At this time, as in the case of writing, there is no waiting for the HDD 6 to rotate, and even during data transfer, the main CPU
processing can be executed.

Furthermore, since the CPU 6 can also realize a disk cache function during reading, disk access performance is greatly improved.

〔Effect of the invention〕

According to the present invention, when accessing a disk in a personal computer, workstation, etc. that has an I5A-AT bus, the load on the main CPU is almost reduced compared to the conventional one, so that other I10s such as communication are
Even after processing, the disk access performance is lower than that of high-speed DM.
A transfer and disk cache functions improve performance by 3 times compared to conventional performance.
It has the effect of improving the performance by more than twice as much.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a file accelerator that is an embodiment of the present invention. FIG. 2 is a diagram showing an example of the system configuration of the present invention, and FIG. 3 is a specific configuration diagram of the bus controller 8 in the embodiment of FIG. FIG. 4 is a conventional system configuration diagram. FIG. 5 is a diagram showing an example of the contents of the register group 9 in the example shown in FIG. 1. FIG. 6 is a diagram showing one embodiment of the contents of the register group 10 in the embodiment shown in FIG. 1. FIG. 7 is a diagram showing data transfer timing in one embodiment of the present invention.

Claims (1)

[Scope of Claims] 1. At least a first CPU (ContralProc
ess-ingUnit) and a file means installed in the computer system, a second CPU and a direct memory access controller (DMAC) are provided between the system and the file means. 1. A file data transfer device characterized in that a file accelerator comprising a bus controller, a register group, and a file accelerator are provided to improve the access performance of the file means. 2. The transfer device according to claim 1, wherein the file accelerator is composed of one semiconductor integrated circuit. 3. The transfer device according to claim 2, wherein the file accelerator includes a register group equivalent to a register group in the file means that can be accessed from the outside. 4. The transfer device according to claim 3, wherein information other than commands can be simultaneously written to the register group according to claim 3 and the register group in the file means. 5. The transfer device according to claim 1, wherein the second CPU has a disk cache function by using a data buffer in the file means as a disk cache memory. 6. The transfer device according to claim 1, wherein the bus controller outputs a signal for selecting the register for data transfer in the file means and a transfer timing signal only during data transfer of the DMAC. . 7. A part of the register group can be written by the first CPU and read by the second CPU, and other parts of the register group can be written by the first CPU.
7. The transfer device according to claim 2, further comprising a configuration in which data can be read from the CPU and written by the CPU.