JPH0442327A - Advance controller - Google Patents

Abstract

PURPOSE:To increase the instruction processing speed by starting the processing of the instruction following to a 1st instruction before this instruction carries out the generation of an address with the use of a register when the outrunning conditions are satisfied. CONSTITUTION:A flip-flop 14 is set when a signal line 305 is set at 0 and held as it is until the output of a signal line 301 is set at 1. Therefore an instruction which is going to generate an address at a stage A is outrun by a subsequent instruction as long as the flip-flop 14 is kept at 1. The flip-flop 15 - 17 carry about the output of the flip-flop 14 at every stage, that is, the instruction of stages O, E and W outrun the instruction of the stage A respectively. Thus the processing can be started for the instructions subsequent to a 1st instruction even though a 1st instruction does not generate any address with the use of a register. Thus, the instruction processing performance is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an advance control device that processes instructions.

[Conventional technology]

In this type of advance control device, if there is a first instruction in which the register number of the register required for address generation matches the register number of the register to be updated by the preceding instruction, the preceding instruction updates the register. until the first instruction performs address generation using registers.
Processing of the instructions following the first instruction is not to be started.

[Problems to be Solved by the Invention] In the conventional advance control device described above, there is a first instruction in which the register number of the register required for address generation matches the register number of the register to be updated in the preceding instruction. In this case, processing of the instruction following the first instruction does not start until the preceding instruction updates the register and the first instruction uses the register to generate an address. The instruction following the first instruction is the first instruction.
If the instruction does not use the information that is updated by executing the instruction, there is a drawback that performance will deteriorate.

SUMMARY OF THE INVENTION An object of the present invention is to provide a proactive control device that can eliminate such drawbacks and prevent performance deterioration in processing instructions.

[Means to solve the problem]

The preceding control device of the present invention includes a first control device that detects whether a register number of a register necessary for generating an operand address of a first instruction matches a register number of a register to be updated in an instruction preceding the first instruction. a determining means; detecting whether the register number of a register necessary for generating an operand address of a second instruction following the first instruction matches the register number of a register to be updated in an instruction preceding the second instruction; a second determination means; a branch instruction identification means for indicating whether the first instruction is a branch instruction; a memory data update instruction identification means for indicating whether the first instruction is an instruction to rewrite memory data; a memory data reference identification means for determining whether or not the instruction refers to memory; a first determination means detects a match; a second determination means detects a mismatch; and a branch instruction identification means detects a first If it is detected that the instruction is not a branch instruction, and the memory data update instruction identification means detects that the first instruction is not an instruction to rewrite memory data, the second instruction is sent to the memory operand before the first instruction. The first one that causes address generation to occur.
The execution means and the first determination means detect a match, the branch instruction identification means detects that the first instruction is not a branch instruction, and the memory data reference identification means determines that the second instruction references memory data. If it is detected that the instruction is not an instruction, the second instruction executes a phrase next to the phrase for generating an operand address before the first instruction.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

The first part is a block diagram showing an embodiment of the present invention.

The advance controller shown in FIG. 1 includes registers 1 to 8.1.
1 to 13, flip-flops 9, 1014 to 17,
Pace register group (BR) 100 and general purpose register group (
GR) 101 and T LB (Translatio
n-Look-asside Buffer) 102, cache 103, and decoder 20
0, selection circuits 201 to 203.220, and control circuit 2
04, comparison circuits 205-211, 216-218, OR circuit 212.219.401, and NOR circuit 2
13, arithmetic unit 214, address adder 215, and A
ND circuits 221 to 226 and signal lines 300 to 305.3
16.

This advance control device is a pipeline type information processing device consisting of five stages D, A, O, E, and W, and the D stage is a stage for decoding the instruction word (000).
The A stage is a stage that reads a register used for address generation and performs address addition. 0 stage is T
L B102. This is a stage where the Cache 103 is indexed and memory data is read out, and the E stage is a stage where an arithmetic operation is performed using the arithmetic unit 214. The W stage is a stage that stores calculation results.

In such a advance control device, register 1 is a register that holds an instruction word. The F field of register 1 defines the operation of the instruction, and the R field indicates the register number of the register to be updated. Furthermore, the B field indicates the register number of the pace register used for address generation, the X field indicates the register number of the general register used for address generation, and the D field indicates the displacement used for address generation. ing.

Decoder 200 decodes whether the instruction word held in register 1 is a branch instruction or not, and outputs it to flip-flop 9 . It also decodes whether the instruction is to store data in the memory or not, and outputs 1 to the flip-flop 10 if the instruction is to store data.

Furthermore, it decodes whether the command is to read memory data or not, and if it is a command to read, outputs 1 to the control circuit 204 through the signal line 300.

Register 2 has a register number of a pace register used for address generation, register 3 has a register number of a general-purpose register, and register 4 has a displacement. Register 5 has the register number of the register updated by the instruction in the A stage. Flip-flop 9 outputs 1 if the instruction in the A stage is a branch instruction;
The flip-flop 10 outputs 1 if the instruction in the A stage is an instruction to store data in memory.

Control circuit 204 sends 1 or 0 to signal line 305 based on the states of signal lines 300 to 304. This situation is shown in the truth table in Table 1 below.

Table 1 (X indicates don't care) Such a signal on the signal line 305 is sent to the flip-flop 14.15 and the selection circuits 201 to 203.220.

The selection circuit 201 selects the B field of register 2 or register I using the signal line 305, and the selection circuit 202
selects the X field of register 3 or register 1 by signal line 305. Further, the selection circuit 203 selects the D field of register 4 or register 1 from the signal line 30.
Select by 5. At this time, if the signal wire 305 outputs 0, the selection circuits 201, 202, 203 select the register l.
Select.

Register group 100 is a pace register group, and register group 101 is a general purpose register group. In addition, the three-man power adder 215 is connected to the outputs of the register groups 100 and 101 and the selection circuit 2.
Address generation is performed using the output of 03 as input.

Register 11 has a memory operand address, and uses the output of register 11 as input to write T L B 102 . C
ache103 is indexed and memory data is read.

The register 12 has memory data, and an arithmetic circuit 214 performs arithmetic operations using the output of the register 12 as an input.

Register 13 is a register that holds calculation results.

Register 5 has the register number of the register updated by the A stage instruction, and register 6 has the register number of the register updated by the O stage instruction. Further, register 7 has the register number of the register updated by the E stage instruction, and register 8 has the register number of the register updated by the W stage instruction.

The flip-flop 14 is 1 if the signal line 305 is 0.
is set and continues to hold 1 until the signal line 303 outputs 0. This indicates that as long as the flip-flop 14 is on, the instruction that has been overtaken by the subsequent instruction is in the A stage.

For flip-flops 15, 16, and 17, the subsequent instructions that overtake the instruction in the A stage are in the 0 stage, respectively.
This indicates that it is in the E stage or W stage.

Next, when an instruction explaining the operation of this advance control device is set in register 1, comparison circuits 208, 209 .
210, 211 and the NOR circuit 213, it is checked whether the R field of the instruction word and the register numbers held in registers 5, 6, and 7.8 match. If there is no match, the NOR circuit 213
1 from the control circuit 20 through the signal line 304.
Notify 4.

In stage A, the comparison circuit 216 checks whether the register number held in register 2 matches the register number held in register 6.

Then, the output of the comparison circuit 216 is transferred to the flip-flop 15.
AND gate 222 performs a logical product with the negative logic output of
Output to circuit 219.

Further, register 2 is compared with register 7 by comparison circuit 217. Then, the negative logic output of the flip-flop 16 and the output of the comparison circuit 217 are ANDed by an AND gate 224 and output to an OR circuit 219.

Further, register 2 is compared with register 8 by comparison circuit 218. Then, the 9 logic outputs of the flip-flop 17 and the output of the comparator circuit 218 are ANDed by an AND gate 226 and output to an OR circuit 219.

Similarly, comparison circuit 205 checks whether the register number held in register 3 matches the register number held in register 6. And comparison circuit 205
The output is ANDed with the negative logic output of the flip-flop 15 by an AND gate 221 and outputted to an OR circuit 212.

Further, register 3 is compared with register 7 by IL comparison circuit 206. Then, the negative logic output of the flip-flop 16 and the output of the comparison circuit 206 are ANDed by an AND gate 223 and outputted to an OR circuit 212.

Further, register 3 is compared with register 8 by comparison circuit 207. Then, the negative logic output of the flip-flop 17 and the output of the comparison circuit 207 are ANDed by an AND gate 225 and outputted to an OR circuit 212.

Next, the OR circuit 401 performs an OR circuit with the output of the OR circuit 219.
The output from the circuit 212 is used as an input, a logical sum is performed, and the output is notified to the control circuit 20.1 through the signal line 303. If the signal line 305 is 0, the flip-flop 14 continues to hold the signal until the output of the signal line 303 becomes 1. As a result, if the flip-flop 14 is 1, this indicates that a subsequent instruction has overtaken the instruction that is about to generate an address in the A stage.

The flip-flops 15, 16, and 17 carry the output of the flip-flop 14 for each stage, and the instructions in the ○ stage, E stage, and W stage are
It shows that you are overtaking the commands on stage.

FIG. 2 is a time chart of the advance control device shown in FIG. 1, and shows timing.

The states of the A, O, E, and W stages and signal lines 100 to 304 are shown. As shown in FIG. 2, instruction 3 uses the register that instruction 2 updates to generate an address, and although instruction 3 is not a branch instruction, it is an instruction that updates memory. In addition, instruction 4 is an instruction that does not index memory,
This is an example in which the register used for address generation is not updated by any of the instructions in the A stage, 0 stage, E stage, and W stage. Since the overtaking condition is satisfied in the To cycle, instruction 4 enters the O stage of the T1 cycle. As a result, instruction A enters the D stage,
It will take 7 machine cycles for both instruction 3 and instruction 4 to complete the W stage. However, in the prior art, the situation is as shown in FIG. That is, FIG. 3 is an example of a time chart of the prior art, in which instruction 3 uses a register updated by instruction 2 to generate an address. Considering instruction 4, from the D stage to the W stage, 8 It will take machine cycles.

In the example shown in FIG. 2, only one instruction overtakes, but it is clear that it is possible for a plurality of instructions to overtake.

In this way, this embodiment adopts a processing method that divides a series of processing steps into a plurality of consecutive phases and has a pipeline that individually and consecutively executes instructions corresponding to each of the plurality of phases. In a pipelined information processing device, a first instruction detects whether a register number of a register necessary for generating an operand address of a first instruction matches a register number of a register to be updated in an instruction preceding the first instruction. Whether the register number of the register required for generating the operand address of the second instruction following the first instruction matches the register number of the register to be updated by the instruction preceding the second instruction. a second determining means for detecting; a branch instruction identifying means for indicating whether the first instruction is a branch instruction; and a memory data update instruction identifying means for indicating whether the first instruction is an instruction to rewrite memory data; a memory data reference identification means for determining whether the second instruction is an instruction that refers to memory; a match is detected by the first determination means; a mismatch is detected by the second determination means;
If the branch instruction identification means detects that the first instruction is not a branch instruction, and the memory data update instruction identification means detects that the first instruction is not an instruction to rewrite memory data, the second instruction is The means for generating a memory operand address prior to the first instruction and the first determining means detect a match, the branch instruction identifying means detects that the first instruction is not a branch instruction, and the memory data reference identifying means detects that the first instruction is not a branch instruction. and means for causing the second instruction to perform the next phase of the operand address generating phrase prior to the first instruction if it is detected that the second instruction is not an instruction that references memory data. This is a special advanced control device.

〔Effect of the invention〕

As described above, the present invention has the effect of speeding up instruction processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart of the embodiment of FIG. 1, and FIG. 3 is a time chart of a conventional advance control device. 1-8, 11-13...Register 9, 10.14-17...Flip-flop 100
...Base register group (BR) 101 ・
...General-purpose register group (GR) 102 . . .
・ ・TLB 103...Cache 200...
... Decoder 2OL 202.203.220 ... Selection circuit 204
...Control circuits 205-211.216-218...Comparison circuit 212
, 219.401...OR circuit 213...
... NOR circuit 214 ... Arithmetic unit 215 ... Address adders 221 to 226 ... AND circuit

Claims (1)

[Claims] (1) a first determining means for detecting whether a register number of a register necessary for generating an operand address of a first instruction matches a register number of a register to be updated in an instruction preceding the first instruction; a second determining means for detecting whether a register number of a register necessary for generating an operand address of a second instruction following the first instruction matches a register number of a register to be updated in an instruction preceding the second instruction; a branch instruction identification means for indicating whether the first instruction is a branch instruction; a memory data update instruction identification means for indicating whether the first instruction is an instruction for rewriting memory data; A memory data reference identifying means determines whether the instruction is a referenced instruction, a first determining means detects a match, a second determining means detects a mismatch, and a branch instruction identifying means determines whether the first instruction is a branch instruction. If it is detected that the first instruction is not an instruction that rewrites memory data, and the memory data update instruction identification means detects that the first instruction is not an instruction that rewrites memory data, the second instruction is caused to generate a memory operand address before the first instruction. 1st
The execution means and the first determination means detect a match, the branch instruction identification means detects that the first instruction is not a branch instruction, and the memory data reference identification means determines that the second instruction references memory data. If it is detected that the command is not an instruction, a second execution means causes the second instruction to execute a phrase next to the phrase for generating an operand address before the first instruction.