JPH0442606B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an apparatus for detecting an abnormality in an incremental encoder. The servo control system applied to robots etc.
It is configured as illustrated in the figure. In this control system, when a command pulse signal is input to a deviation counter 1, a deviation signal corresponding to the number of input pulses is output from the counter 1, and this deviation signal is sent via a digital/analog converter 2 and a servo amplifier 3. to rotate the motor 4. When the motor 4 rotates, the output pulses of the incremental encoder 5 interlocked with the motor 4 are fed back to the deviation counter 1 via the direction discrimination circuit 6, and when the content of the counter 1 becomes zero, the motor 4 stops. In other words, the motor 4 rotates by an amount corresponding to the number of pulses of the command pulse signal and then stops. The speed detector 7 shown in FIG. 1 is provided to obtain a speed feedback signal. By the way, in such a control system, if an abnormality such as a wire breakage occurs in the incremental encoder 5 for some reason, an appropriate position feedback signal cannot be obtained, resulting in problems such as a robot or the like running out of control. An object of the present invention is to accurately detect abnormalities in the incremental encoder and prevent the above-mentioned disadvantages. Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 2 shows an example of the direction determination circuit 6 shown in FIG. As is well known, an incremental encoder uses A, as shown in Fig. 3a and b, which have a phase difference of 90 degrees from each other in order to determine the direction of rotation.
A phase pulse signal S _A and a B-phase pulse signal S _B are output.
The direction discrimination circuit 6 receives these pulse signals S _A and S _B
is input, and when the encoder 5 is rotating in the normal direction, a forward rotation pulse signal + _SF is output, and when it is rotating in the reverse direction, a reverse rotation pulse signal _-SF is output. In the direction discrimination circuit 6 shown in FIG. 2, the differentiating circuit 61 detects the rising edge of the inverted signal _A (see FIG. 3 c) of the A-phase pulse signal S _A obtained by the inverter 62, and A differential signal as shown in FIG. 3e is output and applied to one input terminal of the AND circuit 63. Further, the differentiation circuit 64 detects the rising edge of the signal S _A and outputs a differentiation signal as shown in FIG. The B-phase pulse signal S _B is applied to the other input terminals of the AND circuits 63 and 65, so that when the encoder 5 is rotating normally, the AND circuit 63 outputs a signal as shown in FIG. The forward rotation pulse signal +S _F is outputted, and when the rotation is reversed, the AND circuit 65 outputs a reverse rotation pulse signal -S _F as shown in g in the figure. As shown in Fig. 1, the forward rotation pulse signal +S _F is applied to the down count input terminal of the deviation counter 1, and the reverse rotation pulse signal -S _F is applied to the up count input terminal of the same counter 1. As a result, a feedback loop is formed. FIG. 4 shows another example of the direction determining circuit 6. The direction determining circuit 6 is composed of a 2-bit latch circuit 66, a 4-bit latch circuit 67, and a memory 68 having stored contents to be described later, and operates as follows. That is, each of the latch circuits 66 and 67 has a fifth
The A-phase and B-phase pulse signals S _A shown in Figures b and c,
If a clock signal C _K as shown in a in the same figure, which has a cycle sufficiently shorter than the generation cycle of S _B , is supplied as a sampling signal (latch signal), for example, the logic level of signals S _A and S _B at sampling time Ta will be are "1" and "1", respectively, so the latch circuit 66 latches the states OA="1" and OB="1". And at the next sampling point T〓,
The latch circuit 67 is the latch content of the latch circuit 66.
OA="1", OB="1", and the logic states NA="0" and NB="1" of the signals S _A and S _B at the time T≦ are latched. In this way, the latch circuit 67 controls the logic states OA and OA of the signals S _A and S _B at a certain sampling point.
OB and the logic states NA, NB of the signals S _A , S _B at the next sampling time after this sampling time
Latch. There are a total of 16 combinations of the four states OA, OB, NA, and NB latched by the latch circuit 67, as described below.

[Table] The memory 68 has addresses corresponding to the 16 types of states (OA, OB, NA, NB) shown in the above table, and as shown in the table, data about these addresses -S _F , +S _F is stored. In FIG. 5, when the encoder 5 is in the normal rotation state, the changes in the logic levels of the signal S _A and the signal S _B before and after the rise of the signal S _A are constant. That is, the signal at time Ta and Tc
The logic levels of S _A and S _B are "0" and "0", respectively, and at times Tb and Td, they are "1" and "0", respectively.
It becomes “0”. On the other hand, even when the encoder is reversed, the signal
The logic level changes of the signals S _A and S _B before and after the rise of S _A are constant, and as shown in the figure, they always change from "1" and "0" (times Ta' and Tc') to "0". , changes to "0" (times Tb' and Td'). The logic levels "0" and "0" of the signals S _A and S _B at the above time Ta (Tc) are the states OA and OB, and the logic level "1" of the signals S _A and S _B at the time Tb (Td), Since “0” is latched in the latch circuit 67 as the states NA and NB, in this case, the address signals (OB, OA, NB,
NA) becomes (0, 0, 0, 1), and therefore the +SF signal "0" is output from the memory 68. That is, when the encoder rotates in the normal direction, the direction determining circuit 6 outputs a number of normal rotation pulse signals +SF of logic level "0" corresponding to the amount of rotation of the encoder. Similarly, the address signals (OB, OA, NB, NA) for the memory 68 at times Tb', Td' are (0, 1, 0, 0), so when the encoder 5 is reversed, the logic level is reversed to "0". Pulse signal
The number of S _F corresponding to the amount of rotation of the encoder is outputted from the direction determining circuit 6. By the way, there are the following types of abnormalities in the encoder 5. The A-phase pulse signal remains at "1" and does not change. The A-phase pulse signal remains at "0" and does not change. The B-phase pulse signal remains in the "1" state and does not change. The B-phase pulse signal remains in the "0" state and does not change. Both the A-phase pulse signal and the B-phase pulse signal are no longer output. When the direction determining circuit having the configuration shown in FIG. 2 is applied, if the above-mentioned abnormalities occur, the following states occur, as is clear from FIG. 3. Since the copying signal is no longer output from the differentiating circuits 61 and 64, the signal +S _F ,
-S _F will no longer be output. It is the same as. Since the AND circuits 63 and 65 are always operable, the signal +
S _F and -S _F are alternately output from AND circuits 63 and 65, respectively. Since AND circuits 63 and 65 are turned off, both signals + _SF and _-SF are no longer output. It is the same as. On the other hand, when the direction discriminating circuit having the configuration shown in FIG. 4 is applied, the following states '-' occur in response to the above-mentioned abnormalities. ' Since the states OA and NA are always "1", as is clear from the previous table, both the signals + _SF and _-SF are not output. ' Since the states OA and NA are always "0", both the signals + _SF and _-SF are no longer output. ' Since the states OB and NB are always "1", both the signals + _SF and _-SF are no longer output. ' Since normal OB and NB are always "0", as is clear from the above table and Figure 5,
Regardless of whether the encoder 5 is in the forward or reverse direction, the signals +S _F , -
S _F will be output alternately and each with the same period as signal S _A. ' Since the states NA, NB, OA, and OB are always "0", both the signals + _SF and _-SF are not output. The above state, , and ′, ′, ′,
When ' occurs, the feedback pulse in the control system shown in FIG. 1 disappears, causing the robot to run out of control. Furthermore, when states and ' occur, the signals + _SF and _-SF will appear alternately as feedback signals regardless of the robot's operating direction.
As expected, the robot will go out of control. FIG. 6 shows an embodiment of an abnormality detection device according to the present invention that detects abnormalities in the encoder 5 described above. The abnormality detection device according to this embodiment includes a flip-flop 8 which receives the output signals +S _F and -S _F of the direction discriminating circuit 6 at its set input terminal and reset input terminal, respectively, and a high-pass circuit which receives the output signal of this flip-flop 9. A filter 9, an OR circuit 10 which inputs each of the above-mentioned signals +S _F and -S _F , a re-trigger type timer circuit 11 which is triggered by the output of this OR circuit, and an output of the above-mentioned filter 9 and the timer 11. and an OR circuit 12 which performs the logical OR of the outputs of the . In the control system shown in FIG. 1, the following three states are possible for the robot. 1) Proceeds in the + direction 2) Proceeds in one direction 3) Stops When the encoder is normal, the robot moves 1)
When under the state _of
When the circuit is under the condition 2), the circuit continuously outputs the signal _-SF . In addition, under the condition 3), the robot moves slightly until the feedback pulse is returned, which is usually called a limit cycle. The signal +S _F and the signal -S _F are output alternately at regular intervals. The components of the high-pass filter 9 are set so as to pass a signal having a cycle shorter than the generation cycle of the signals + _SF and _-SF during the limit cycle. In addition, the timer circuit 11
is composed of a retrigger type one-shot circuit, etc., and its setting time is set to be larger than the generation cycle of the signals + _SF and _-SF during the limit cycle. Therefore, during the limit cycle, the timer circuit 11 is retriggered while counting time, so that the logic level at its output terminal remains at "0". The operation of this embodiment will be explained below. When the encoder 5 is normal and the robot is in the state 1) or 2), the flip-flop 8 continues to be in the set state or the reset state, so no signal is output from the high-pass filter 9. Also, timer 11 uses the above signal +S _F or -S _F
Since both triggers occur before the timing operation ends, no signal is output. Next, when the robot is in the state 3), the flip-flop 8 alternately repeats setting and resetting, but since the cycle is extremely long, the output signal is removed by the filter 9. Furthermore, as described above, the timer circuit 11 is triggered by the signals +S _F and -S _F before its timekeeping operation is completed, and therefore does not output a timekeeping end signal. Thus, when the encoder is normal, the output terminal of the OR circuit 12 maintains the logic level "0". Next, when the above-mentioned states , , , , , , and ′, ′, ′, and ′ occur due to an abnormality in the encoder 5, and both the signals + _SF and _−SF are no longer output from the direction determination circuit 6, the timer 11 is restarted. Since the trigger is not activated, the timer outputs a signal of logic level "1", and as a result, the OR circuit 12 outputs an alarm signal "1". Further, due to an abnormality in the encoder 5, the above-mentioned states and '' are caused, which causes the signals +S _F and -
When S _F begins to appear alternately in short cycles, the flip-flop 8 repeats the setting and resetting operations at high speed. Therefore, flip-flop circuit 8
The output signal is outputted via the high-pass filter 9, and thereby the OR circuit 12 outputs an alarm signal. In this way, the flip-flop 8 functions as a means for detecting the state in which the signals + _SF and _-SF alternately appear, and the filter 9 functions as a means for detecting a state in which the signals +SF and -SF alternately appear, and the filter 9 has a constant period of the signals + _SF and _-SF that alternately appear. It functions as a means for determining whether or not the above is true. Further, the OR circuit 10 and the timer circuit 11 input the above-mentioned signals +S _F , -
It functions as a signal presence/absence determination means for detecting that both SF and _F do not occur for a certain period of time. Note that the alarm signal output from the OR circuit 12 is used to command the robot to stop or to indicate an abnormality. Furthermore, in the embodiment described above, the high-pass filter 9 determines whether the clip-flop 8 is set and reset in a long cycle or in a short cycle. By combining a frequency/voltage converter and a comparator (both not shown) that determines whether the output of the converter is above a predetermined value, these can be substituted for the filter. As is clear from the above embodiments, according to the present invention, an abnormality in an incremental encoder can be accurately detected by a simple means, and its practicality is extremely high.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of a servo control system applied to robots, etc., Figure 2 is a block diagram showing an example of a direction discrimination circuit, and Figure 3 is the direction discrimination circuit shown in Figure 2. FIG. 4 is a block diagram showing another example of the direction discrimination circuit, FIG. 5 is a timing chart explaining the operation of the direction discrimination circuit shown in FIG. 4, and FIG. 1 is a block diagram showing an embodiment of an abnormality detection device according to the present invention. 5... Incremental encoder, 6... Direction discrimination circuit, 8... Flip-flop, 9... High pass filter, 10, 12... OR circuit, 12... Timer circuit.

Claims (1)

[Claims] 1. A state detection means for detecting a state in which a forward rotation pulse signal and a reverse rotation pulse signal appear alternately from a direction discrimination circuit, and a period of the alternately appearing signals is constant when the state is detected. An abnormality detection device for an incremental encoder, comprising period determination means for detecting the above and outputting an abnormal signal. 2. An abnormality detection device for an incremental encoder according to claim 1, wherein the state detection means is a flip-flop. 3. The abnormality detection device for an incremental encoder according to claim 1, wherein the period determining means is a high-pass filter. 4 The period determination means is a frequency/voltage converter,
An abnormality detection device for an incremental encoder according to claim 1, comprising a comparator for detecting that the output voltage of the frequency/voltage converter is above a certain level. 5. A state detecting means for detecting a state in which a forward rotation pulse signal and a reverse rotation pulse signal appear alternately from a direction discrimination circuit, and detecting that the cycle of the above-mentioned alternately appearing signals is equal to or greater than a certain value when the state is detected. Abnormality detection of an incremental encoder, comprising: a cycle determining means for outputting an abnormal signal when the forward rotation pulse signal or the reverse rotation pulse signal is detected for a predetermined period of time; Device. 6: an OR circuit in which the signal presence/absence determining means takes a logical sum of the forward rotation pulse signal and the reverse rotation pulse signal;
6. The abnormality detection device for an incremental encoder according to claim 5, which is a re-trigger type timer circuit triggered by the output signal of the OR circuit.