JPS61214031A - Interruption processing method of microcomputer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an interrupt processing method for a microcomputer, and is particularly suitable for controlling servomechanisms, robots, and the like.

BACKGROUND OF THE INVENTION Conventionally, control of servomechanisms, for example, precise control of the rotational speed of a motor, has been achieved by hardware, but in recent years, with advances in microcomputers, it has also been achieved by software. A method of controlling the motor is to attach a rotary encoder to the motor, generate pulses proportional to rotation, and give acceleration and deceleration commands to the motor so as to keep the intervals between the pulses constant. Therefore, in this case, it is extremely important for the microcomputer (hereinafter abbreviated as microcomputer) to accurately know the pulse timing, and this determines how precisely control can be performed.

Most microcontrollers do not have a function to directly detect pulse timing, but Intel's 1-chip microcomputer MC896, for example, detects the edges of input signals as shown in Figure 7. It is now possible to memorize the timing.

This will be explained below based on FIG. Each input signal (1 to 4
) is sent to FIFO (
First In First Out) 706. Similarly, the output of the n-bit counter 705 is F.
It is input to IFO706. Therefore P I
The bit width of F0706 is n+4 bits. input 1
When any one of .about.4 changes, the input signal value and the n-bit binary counter value are written to the FIFO 706. That is, the changed signal information and the time at that time are stored in the FIFO 706. When the amount of information stored in the F I FO 706 increases, an interrupt request signal is issued,
Generates an interrupt to the cpU (not shown). For interrupt processing, the FIFO 706 is read out in order and processing is performed accordingly. Thereby, the time at which the input signals 1 to 4 change can be easily known.

Problems to be Solved by the Invention In the conventional example, in the P I FO 706, the sum of the number of bits of the counter and the total number of bits of the input signal was required for all stages. Therefore, as the types of input signals increase, the P I FO706
The disadvantage is that the capacity is very large.

Furthermore, since FIFO is used, processing will be delayed by the number of stages. In particular, even if inputs with different priorities arrive at almost the same time, they can only be processed in the order of the time they arrived, and the software is complicated to ensure that the processing of inputs with higher priority is not delayed. I'm going to change it.

Means for Solving the Problems In order to solve the above problems, means for storing the value of the n pino h counter is provided in accordance with each input signal, and further means for storing changes in each input signal. is provided, and an interrupt is issued to the CPU in response to a change in at least one of the input signals.

It has an n-bit counter for counting the operating clock, and has j means for detecting, in synchronization with the clock, that each of the j external input signals has changed to a valid level. , the output signal from the detection means determines the n
j number of output-controllable n-bit latches for respectively latching the output value of the bit counter, and j number of output-controllable flip-flops each set by an output signal from the detection means; The output, the reset input, and the output of the n-bit latch are connected to the data bus of the microcomputer, and data can be read and written by specifying an address. Furthermore, the output signals from the input signal change detection means are logically summed, and the
Since the CPU has a means for generating an interrupt request to the PU, in interrupt processing, the CPU reads the outputs of the j 7IJ round flops onto the data bus and performs processing corresponding to the set flip 70 round. Resets the set slip-flop through the data bus. Thereby, the CPU can immediately and easily know which signal changes and when among the j input signals.

Embodiment An embodiment of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing a schematic configuration of the present invention.

External input signals 1 to 4 are input to logical differentiation circuits 1 to 4, respectively, and are also input to a level change detection (a kind of differentiation) circuit 11, and are further connected to the output of CPU interrupt 7 \ circuit 5. . Therefore, the value of the logic] counter is latched. Even if a differential pulse is generated at the same time, the corresponding launch is activated at the same time.

On the other hand, the factor flag 11 is set by the differential pulse to the corresponding R
-S flip-flop is set. Furthermore, the CPU
The interrupt request pulse generation circuit 12 has functions, can turn off the output, and can be directly connected to the data bus. Similarly, the output of the factor flag 11 can also be directly connected to the data bus. Furthermore, in the factor flag 11, it is also possible to reset the flip-flop through the data bus, and the data bus is bidirectional.

To switch the data input/output of this data bus, the CPU sends an address, and the address decoder 13 determines which latch output is enabled (on), and whether the flip-flop of the cause flag is read or reset. This is to switch between.

The specific configuration of each block will be explained below. FIG. 2A is a circuit diagram showing the configuration of logic differentiating circuits 1 to 4. This circuit detects the rise and fall of an input signal that is not synchronized with the clock, and outputs a pulse with a width corresponding to % of the clock at the time of detection. The input signal is input to the D input terminal of the D flip-flop 21 and the AND circuit 22 without being switched.

When the input signal becomes High level and the clock rises, the D flip-flop 2 goes high, as shown by al in Figure B.
The Q output of 1 becomes Low level. This state is held until the clock rises after the input signal goes low again. The Q output of the slip-flop 21 and the input signal are input to an AND circuit 22. Therefore, as shown in FIG. 2B, the output a2 of the AND circuit 22 maintains a high level during the period from when the input signal rises to when Qal falls in synchronization with the clock. The output a2 of the AND circuit 22 is input to the D terminal of the D flip-flop 23. Therefore, D flip 92,-.

The Q output of the flop 23 is at a low level for only one clock period, as shown at d3 in FIG. Furthermore, the Q output of the D flip-flop 23, the clock and the -1NOR circuit 24
High for only half the clock by inputting
Obtain an output that becomes h level. In this way, a falling edge of the input signal can be detected and a corresponding pulse can be output.

Next, FIG. 3A (d) is a circuit diagram showing the configuration of an n-bit latch. Outputs Q1, Q2 of the n-bit counter
...Qn is the D of each D flip-flop 30 to 34
connected to the terminal. - Brave flip 70 Tsubu 30
The output pulse of the logic differentiator circuit explained in FIG. 2 enters the clock terminal T of .about.34. Therefore, when the differential pulse rises, each D flip-flop 30-34 outputs the counter output value Q1. Q2.・・・・・・
- Qn is launched, and its held value can be read from each Q terminal. As shown in FIG. 2B, this differential pulse has a phase opposite to that of the counter clock, so that it does not overlap with the timing at which the counter value changes. Now, 10, the output terminals Q of each flip-flop 3o to 34 are all 3
It is connected to the data bus via state banffs 736-40. The control inputs of three-state buffers 36-4o are controlled by latch read address signals. That is, only when a signal to select this latch is issued, the output values of the D flip-flops 30 to 34 are transferred to the data buses D1 to D1.
It will be on Dn.

FIG. 4 is a circuit diagram showing the configuration of the factor flag.

Each output of the logic differentiator shown in FIG. 2 is input to each S terminal of the corresponding RS flip-flops 41 to 44. Therefore, when an output pulse from the logic differentiator is input, the corresponding RS flip-flop is set. The output Q of each R8 flip-flop 41-44 is connected to a data bus via 3-state buffers 46-48, respectively. A factor flag read address signal is connected to the control terminal of the 3-state buffer, and by sending an address for selecting read of the factor flag,
117 of the output Q of each R3 flip-flop.

One data is placed on the second data bus. Furthermore, each line of the data bus is input to AND gates 49-52. A write permission signal is input to the other input of each AND gate 49-52.

This write permission signal is obtained as an output signal by inputting a write pulse signal and a factor flag write address signal to an AND circuit 63.

That is, when the cause flag write address is sent out, data with the bit corresponding to the RS flip-flop to be reset set to High is sent out on the data bus, and the write pulse signal is raised, the RS flip-flops 41 to 4
Any one of the four can be reset.

FIG. 6A is a circuit diagram showing an example of a CPtJ interrupt request signal generation circuit, and is particularly a configuration example when added to a 1-chip microcomputer. The output signals of each logic differentiator circuit shown in FIG. 2 are inputted to an OR circuit 6o to obtain a composite differentiated pulse signal. Depending on the type of microcomputer, this composite differential pulse may be used directly as an interrupt request signal. However, when adding it to a 1-chip microcombicoater, the width of this differential pulse may be too narrow to cause an interrupt to the CPU.

In order to prevent the CPU from being interrupted by noise or the like, if the width of the interrupt pulse is narrow, the interrupt is not accepted. Therefore, in this case,
It is necessary to widen the width of the interrupt request pulse. A self-stop counter composed of an OR circuit 63 and T flip-flops 61 and 62 is a circuit for this purpose. z-1
, the counter is assumed to be in a stopped state. That is, T
Output Q b 2 of flip-flop 62 High
V shall be in Hell. Since this signal is input to the OR circuit 63, the output b3 of the OR circuit 63 is High.
h level, and the T flip-flop 61 cannot be inverted. Therefore, the counter does not work. Here, when the composite differential pulse b 1 reaches a high level, the T flip-flops 61 and 62 are reset. Therefore, the output Qba of the T flip-flop 61 and the output b2 of the T flip-flop 62 are all at Low level 13, . . . -full. Therefore, the clock input that was prohibited by the OR circuit 63 is input to the T flip-flop 61. When this input b3 falls twice, the output Qb2 of the T-clip front pro 2 becomes High level, so
When the level becomes High, the input signal is no longer input to the T-flash flip flop 61, and the counter stops. Therefore, the output Qb2 of the T flip-flop 62 is kept at Low level only during this period. FIG. 5B shows this timing. If the synthesized differential pulse is not synchronized with the clock, the resulting output pulse width will be between the equivalent of one clock and the equivalent of two clocks, and the width will not always be the same, but this does not pose a particular problem in the present invention. Figure B
Also, tl and t2 are clearly not equal. This is because the output value of the n-bit counter is used as the clock input to the OR circuit 63 in order to simplify the circuit. By using this signal,
The number of T flip-flops is only two. Thus, by using a relatively slow clock 14, the pulse width can be extended, creating an interrupt request pulse that is clearly distinguishable from noise.

Figure 6 shows the hardware described so far.
3 is a flowchart showing an interrupt processing procedure in a CPU. When the CPU accepts an interrupt, it first reads the cause flag and checks what signal caused the interrupt to be accepted. (Block 7o0) Next, each flip-flop is checked using the read factor flag, and if the flip-flop is set, processing is performed according to the factor. First, in block γ1, if the flip-flop of factor 1 (corresponding to input 1) is set, block 72 processes the factor (for example, reads the corresponding n-bit latch value and calculates the difference from the previous value). (processing such as calculating the pulse period), and in block 73, the flip-flop of factor 1 is reset. block 71
If the flip-flop of factor 1 is not set in , the process proceeds to blocker 4 without doing anything. block 74
,75°15. At 76, the same processing as for factor 1 is performed on factor 2. Similar processing is performed for all factors, and CP
U ends the interrupt processing. Particularly in this case, even if many factors enter at the same time, processing can be easily performed starting from the factor with the highest priority. In the example of FIG. 6, factor 1 has the highest priority.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention overcomes the drawbacks of the prior art. First, the number of flip-flops increases less as the input signal increases. This is conventionally (n + j)
j pieces were required, but in the present invention, it can be realized with a small number of (n+1)Xi pieces. (n is the number of bits of the counter and latch, and j is the number of input signals.) Furthermore, in the present invention, it is possible to perform processing such as performing force processing first, which enables highly accurate control. It has many effects, such as being easy to apply in various fields.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the hardware configuration of an embodiment of the present invention, FIG. 2A is a circuit diagram showing an example of the configuration of the logic differential circuit in FIG. 1, FIG. A is a circuit diagram of the n-bit latch in FIG. 1, B is its timing diagram, FIG. 4 is a circuit diagram showing an example of the configuration of the factor flag in FIG. 1, and FIG. 5A is a circuit diagram of the n-bit latch in FIG.
FIG. 6 is a circuit diagram of a U interrupt request pulse generating circuit, FIG. 6 is a timing diagram thereof, FIG. 6 is a flowchart showing a CPU interrupt processing procedure, and FIG. 7 is a block diagram showing a hardware configuration in a conventional example. 1.2, 3.4...Logic differential circuit, 5...
n bi, counter, 6171'1i1110. ,,,
,, n-bit latch, 11... factor flag,
12...CPU interrupt request pulse generation circuit.

Claims (1)

[Claims] It has an n-bit counter that counts clocks, and has j means for detecting, in synchronization with the clock, that each of j external input signals has changed to a valid level, and j number of output-controllable n-bit latches that each latch the output value of the n-bit counter by the output signal from the detection means; and j number of output-controllable latches that are individually set by the output signal of the detection means. It has a flip-flop, and the output of the flip-flop, its reset input, and the output of the n-bit latch are connected to a bidirectional data bus, and are set so that they can be read and written by specifying an address, respectively. It has means for calculating the logical sum of the output signals from the input signal change detecting means and generating an interrupt request to the CPU based on the logical sum output, and the CPU receives the contents of the one flip-flop from the data bus in interrupt processing. An interrupt processing method for a microcomputer, characterized in that interrupt processing corresponding to a read and set flip-flop is performed, and the set flip-flop is reset by a data bus.