JPH0442660A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To reduce the frequency of an oscillation circuit to obtain a final clock while keeping the accuracy without use of a delay line by adopting the configuration of the circuit comprising plural frequency divider circuits and a simple logic circuit and frequency dividing an input clock frequency into one over a prescribed number and outputting the result. CONSTITUTION:An output pulse synchronously with an input synchronously with Si in a prescribed timing is formed from plural clocks CK1 - CK4 with different phases and the input synchronizing signal Si. The plural clocks CK1 - CK4 are frequency-divided into 1/N synchronously with the output pulse, and gate signals r - u among plural output pulses j - m are fed to a gate means gating a frequency division output synchronously with the input synchronizing signal Si among obtained plural frequency division outputs j - m. Thus, the fundamental frequency to obtain a data clock is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous circuit suitable for application to laser printers and the like.

[Background of the Invention] An image processing device, such as a digital copying machine using a laser printer, is composed of a scanner part (surface image reading part) 30, an image processing part 40, and a printer part 10, as shown in FIG. ing.

By driving the image reading unit 30 to optically scan the original 20, the image information of the original 20 is converted into an optical image, which is supplied to the image processing unit 40, where it is converted into an image signal and subjected to predetermined image processing. I can run out.

Image processing includes enlarging/reducing processing, hatching processing, hollow processing, etc., and in the case of color composition, color ghost correction processing.

In the printer section (laser printer) 10, the image processing section 4
An image is recorded based on a digital image signal (It image data) of predetermined bits formed by 0.

FIG. 5 shows an example of the printer section 10.

In this example, an electrophotographic printer using a photoreceptor drum is used, and a laser beam is used as a light source for forming an electrostatic latent image.

In the same figure, the image data DATA that can be output from the image processing section 40 is completely supplied to the modulation circuit 50, and the image data DATA
A signal based on the TA is formed.

A signal from the modulation circuit 50 is supplied to the semiconductor laser 31 via the laser drive circuit 32, thereby recording an image.

The laser driving circuit 32 is controlled by a control signal from the timing circuit 133 so that it is in the driving state only in the horizontal and vertical effective sections.

A signal indicating the amount of laser beam light is fed back from the semiconductor laser 31 to the laser drive circuit 32, and the drive of the semiconductor laser 31 is controlled so that the amount of light is constant.

A laser beam output from the semiconductor laser 31 is supplied to a polygon mirror 35 and deflected.

The scanning start point of the laser beam deflected by the polygon mirror 35 is detected by the index sensor 36, and the detection signal is converted into a voltage signal by the current-voltage conversion amplifier 37 to generate the index signal (input synchronization signal) St. It is formed.

This index signal S1 is supplied to the synchronization circuit 60. The synchronous circuit 60 is supplied with a clock CK having a predetermined frequency from the oscillation circuit 55, and this clock CK has a frequency of 1/N (N
is an integer, for example, N=2.4), and a divided output DCK synchronized with the index signal Si is output.

This frequency-divided output DCK will be supplied to the modulation circuit 50 as its data clock.

34 is a motor drive circuit that rotates the polygon mirror 35, and its on/off control signal is sent to a timing circuit 33.
Supplied from.

FIG. 6 is an example of an image exposure system (laser beam scanner) in which a laser beam forms an image.

The laser beam emitted from the semiconductor laser 31 passes through mirrors 42 and 43 to the polygon mirror 35 described above.
is incident on the The laser beam is deflected by the polygon mirror 35, which is used for imaging f/ which regulates the beam diameter.
The surface of the photoreceptor drum 47 can be completely irradiated through the θ lens 44.

Note that 45 and 46 are cylindrical lenses for negative tilt correction.

Here, the laser beam scans the surface of the photoreceptor drum 47 at a constant speed in a predetermined direction a by the polygon mirror 35, thereby performing exposure corresponding to image data and forming an electrostatic latent image.

Then, toner charged with the opposite polarity is attached to this electrostatic latent image and development is performed, and then a recording paper is superimposed on the toner image, and a corona charger is applied from the back side of the recording paper.The polarity of the corona charge is as follows. A toner image is transferred to the recording paper by applying charges of opposite polarity to the recording paper.

By the way, as mentioned above, the data clock DCK that can be supplied to the modulation circuit 50 is generated from the index signal Si (horizontal synchronization signal) obtained by scanning the laser beam. Representative means are known.

The frequency division method employs the means shown in Japanese Patent Publication No. 58-32545, for example, in which a high frequency signal that is an integral multiple of the target clock frequency is divided to form a predetermined data clock DCK. ing.

Further, as a typical configuration of the selection method, there is a configuration disclosed in Japanese Patent Publication No. 63-41466, for example.

This selection method is configured to divide a clock cycle into equal intervals by precision delay lines, and select a clock delay signal that has a relationship with a predetermined index signal.

[Problem H to be solved by the invention] When adopting the frequency division method in the conventional example described above, for example, a clock frequency of 15.27 MHz is obtained as the data clock DCK, and an accuracy of 1/8 pixel is obtained. Therefore, the basic oscillation frequency is 122.16MH
It becomes z.

As described above, the frequency division method requires a high oscillation frequency to improve accuracy, and has the disadvantage that the synchronization circuit becomes complicated.

In addition, when using the selection method, the data clock DC
The clock frequency of K is 15.27MHz, 1/8
In order to obtain pixel accuracy, a delay line of approximately 8° and 186 nsec is required.

Then, it is necessary to prepare a delay line with an appropriate delay time to divide one clock at equal intervals equal to one cycle accuracy, but it is extremely difficult to obtain such a delay line. This also causes an increase in the cost of the synchronous circuit.

Therefore, this invention solves these problems and proposes a synchronization circuit that operates by lowering the fundamental frequency to obtain a data clock while maintaining accuracy without using a delay line. It is.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a phase difference generating means for generating a plurality of clocks having different phases, a plurality of clocks, and a method for generating a plurality of clocks and an input synchronization signal from an input synchronization signal. a pulse forming means that outputs an output pulse synchronized with a fixed timing, and a plurality of clocks that divide a plurality of clocks into 1/N (N is an integer) in synchronization with the output pulse output from the pulse forming means. a gate means for gating the divided output synchronized with the input synchronization signal among the plurality of divided outputs obtained from the plurality of frequency dividing means; and a gate signal for the gate means from the plurality of output pulses. The invention is characterized in that it is comprised of a gate signal forming means.

[Function] The index signal Si can be used as the input synchronization signal, and a plurality of clocks with different phases are formed using a single basic clock CK (=CKl).

The phase difference generating means 62 outputs four clocks GKI to CK4 each having a phase difference of 90 degrees (FIG. 2 BE).

These clocks CKI to CK4 and index signal S1
is supplied to the D-type flip-flops 71 to 74, and from this, the flip-flop outputs f −i shown in FIG.
can be output.

Flip-flop output f −i and index signal Si
is an OR circuit 81 that roughly operates as a logical sum in terms of its logical configuration.
.
The first pulse jm shown at H is output.

In the case of FIG. 2, among these first pulses j −, -m,
Since only the first pulse j is inverted to low level, it can be output as a pulse synchronized with the clock CKI. This is because, as is clear from FIGS. 2A to 2E, the first clock input to the index signal Si is CKI (however, the condition for the first input is based on the rising edge of the clock). ).

The earliest pulses j to m, together with clocks CK1 to CK4,
It is supplied to D-type flip-flops 86-89. The outputs V to y (V to Y in FIG. 2) are supplied to AND circuits 91 to 94.

These AND circuits 1191 to 94 are supplied with a gate signal r''-u (FIG. 2 R
-U) is supplied. This gate signal r''-u is
AND outputs n to q formed from the above-mentioned earliest pulses j -, -m and these earliest pulses j to m (Fig. 2 N-Q)
formed based on.

As a result, when the earliest clock CKI for the index signal Si is input as shown in FIG. Figure Z).

In the case of FIG. 3, since the first clock input to the index signal Si is CK3, only the gate circuit 93 enters the gate state in synchronization with this clock CK3, and the signal is output from the D-type flip-flop 88. Divided output
will be used as the data clock DCK (
(See Figure 3).

〔Example〕

Next, the 11th! This will be explained in detail with reference to I and below.

In the present invention, an example is exemplified in which the index signal Si can be used as the input synchronization signal, and four clocks CKI to CK4 each having a phase difference of 90 degrees are used as the plurality of clocks having different phases.

Therefore, the synchronous circuit 6o shown in FIG. 1 is provided with an oscillator 61, and a clock CK (=CK1) of a predetermined frequency obtained from the oscillator 61 is supplied to the phase difference generating means 62.

The phase difference generating means 62 has a delay circuit 64 and an input clock C.
An inverter 63 that inverts the phase of clock CK2, and an inverter 6 that inverts the phase of clock CK2 output from the delay circuit 64.
5 and amplifiers 66 and 67.

Therefore, with the clock CK1 outputted from the amplifier 66 as a reference, the amplifier 67 outputs the clock CK2 whose phase is delayed by 90 degrees, and the inverter 63 outputs the clock CK2 whose phase is 180 degrees different from the clock CKI.
3 is fully output, and the clock CK4 having a phase difference of 270 degrees is output from the inverter 65 (Figure 2 B-E).
reference).

Four clocks CKI with different phases of 90 degrees like this~
CK4 can be supplied to the clock terminals of D-type flip-flops 86 to 89, which constitute the frequency dividing means 85 in this example. These D-type flip-flops 86 to 89 use the output outputted from their inverting output terminals as input data D. Therefore, in this example, the clock CK can be divided in half (N= 2).

On the other hand, an index signal St is supplied to the input terminal 75, and this index signal Sf and the above-mentioned four clocks CKI to CK4 are supplied to the Kani pulse forming means 70.

The foremost pulse forming means 70 includes four thin D-type flip-flops 71 to 74 and OR circuits 81 to 84 that perform an OR operation.
Consists of.

An index signal St is commonly supplied to the data input terminals of the D-type flip-flops 71 to 74 via an amplifier 76, and a clock CKI is supplied to the D-type flip-flop 71 as its clock signal. Similarly, clocks CK2 to CK4 are supplied to D-type flip-flops 72 to 74, respectively.

The four D-type flip-flops 71 to 74 have flip-flop outputs f −, -i as shown in FIG.
can be output.

The flip-flop output f-i and the above-mentioned index signal Si have their phases inverted by an inverter 77 and are supplied to OR circuits 81-84.

In this case, the index signal St is the OR circuit 81 to 84
Commonly supplied to Then, from OR time 1881, clock CK1. In addition to the index signal Si, flip-flop output f (inverted output) + g, so that the pulse corresponding to the CK2O phase difference is output as the first pulse,
i is in full supply.

Thereafter, the flip-flop outputs f*g (inverted output) and h are similarly supplied to the OR circuit 82, respectively.

The OR circuit 83 has a flip-flop output g*h
(inverted output) ++ is supplied, and the final stage OR circuit 84 is supplied with flip-flop outputs i (inverted output), f, and h, respectively.

Therefore, as shown in FIGS. 2A to 2E, when the rising edge of the clock is used as a reference, the first clock input to the index signal Sf is III! Since the clock CKI is indicated by IB, in this case, the first pulse j (J in FIG. 2) output from the OR circuit W881 is used as the first pulse.

These earliest pulses j=m can be supplied to the gate signal forming means 100.

As shown in the figure, the gate signal forming means 100 includes RS flip-flops 101 to 104 and AND circuits 106 to 109 provided on their reset terminal sides for AND operation.
The first pulses J-, -m can be supplied to the set terminal, and the AND circuits 106 to 109
is supplied with the earliest pulse other than the earliest pulse supplied to the set terminal. Therefore, the AND circuit 106~
109 is a 3-man power, 1-output configuration.

As a result, as shown in FIG. 2J, if the first pulse j is obtained only in the OR circuit 81, the AND output n%q becomes N-Q in FIG. 2, so only the RS flip-flop 101 is reset. be done. As a result, the gate signals r to U shown in FIG. 2 are outputted from each output terminal Q of the RS flip-flops 101 to 104.

These gate signals r to U are respectively supplied to AND circuits 91 to 94 constituting the gate means 9o, and the output yy from the frequency dividing means 85 is supplied to the other one.

Here, the D-type flip-flops 86 and 89 constituting the frequency dividing means 85 are supplied with four clocks CKI to CK4 having different phases as described above, and the corresponding earliest pulses are supplied as reset pulses. j to m are supplied.

As a result, since only the D-type flip-flop 86 can be reset by the first pulse j as described above, the output V obtained by dividing the clock CKI input thereto becomes an output synchronized with the first pulse j.

Since this earliest pulse j is also synchronized with the index signal Si, the frequency-divided output V is finally obtained as an output synchronized with the clock CKI input first into the index signal Si. Since this frequency-divided output V is outputted via the AND circuit 91 and the OR circuit 95, this frequency-divided output V is used as the data clock DCK (Z in FIG. 2).

As described above, when the first clock input to the index signal Sf is CKI, the divided output V obtained by dividing this clock CKI into half is the data clock synchronized with the index signal Si. The signal is supplied as DCK to the modulation circuit 50 described above.

FIG. 3 is a waveform diagram showing another example.

In this example, the third clock CK3 is the index signal S
This is the case where input is first made to i, and the first rising pulse is obtained corresponding to this third clock CK3 (third
Figure L).

As a result, since only the AND output p (P in the same figure) remains at a high level, only the gate signal t (T in the same figure) outputted from the third RS flip-flop 103 is inverted to high level, thereby causing the third RS flip-flop 103 to invert to a high level. Only the AND circuit 93 is in the gate state.

Therefore, the output X (X in the figure) obtained by dividing the clock CK3 input to the third D-type flip-flop 88 into half is gated and can be used as the data clock DCK (FIG. 2).

In this way, in both cases of Fig. 2 and Fig. 3,
A frequency-divided output synchronized with the first input clock is obtained for the index signal St, and this is the data clock D.
It will be used as CK.

In the synchronous circuit 60 shown in FIG. 1, the basic clock CK can be divided in half by using only a simple logic circuit configuration and the 1/2 frequency dividing means 85.

Therefore, as mentioned above, in order to use 15.27 MHz as the frequency of the data clock DCK and obtain an accuracy of 1/8 pixel, the oscillation frequency of the clock CK output from the oscillator 61 must be 2 MHz. It would be sufficient to use twice the frequency.

Although the first pulse synchronized with clock CKI or CK3 has been described above, other clocks CK2.
It is easy to understand that the first pulse synchronized with CK4 also operates in a similar manner.

Furthermore, in the above, the pulse forming means for obtaining an output pulse synchronized at a constant timing with respect to the index signal Si, which is an input synchronization signal, is designed to obtain an output pulse synchronized with the index signal Si at the fastest timing. But this is just an example.

In the above description, an example has been described in which the synchronous circuit 60 according to the present invention is used as a synchronous circuit in a printer unit 10 as shown in FIG. It's not easy to run a business.

[Effects of the Invention] As described above, according to the present invention, the input clock frequency can be divided into a predetermined number and output by using the configuration of a plurality of frequency dividing circuits and a simple logic circuit.

Therefore, in the present invention, it is possible to lower the frequency of the oscillation circuit used to obtain the final clock while maintaining accuracy without using a delay line.

As a result, according to the present invention, the structure of the oscillation circuit itself can be simplified, and since an expensive delay line is not used, the cost can be significantly reduced compared to the conventional structure.

Therefore, the synchronous circuit according to the present invention is suitable for application to the above-mentioned synchronous circuit for laser printers.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an example of a synchronous circuit according to the present invention,
Figures 2 and 3 are waveform diagrams to explain the operation, Figure 4 is a system diagram showing an example of image processing, Figure 5 is a system diagram showing an example of the printer section, and No. 6m is an example of a laser beam scanner. FIG. 10 ・ ・ 20 ・ ・ 30 ・ ・ 31 ・ ・ 40 ・ ・ 50 Fist ・ 60 ・ ・ 61 ・ ・ 62 ・ ・ 70 ・ ・ 85 ・ ・ ・Printer section・Document・Part of scanner・Semiconductor laser・Image processing section・Photosensitive drum, modulation circuit, synchronization circuit, oscillator, phase difference generation means, first pulse forming means, frequency dividing means 90...gate means 100...gate signal forming means FIG.

Claims (1)

[Claims] (1) A phase difference generating means for generating a plurality of clocks having different phases; and a pulse forming means for outputting an output pulse synchronized with the plurality of clocks and an input synchronization signal at a constant timing with respect to the input synchronization signal. , the plurality of clocks are 1/1/1 in synchronization with the output pulse output from the pulse forming means.
a plurality of frequency dividing means for dividing the frequency by N (N is an integer); a gate means for gating the divided output synchronized with the input synchronization signal among the plurality of frequency divided outputs obtained from the plurality of frequency dividing means; A synchronous circuit comprising gate signal forming means for forming a gate signal for the gate means from the plurality of output pulses.