JPH0442693A - Frame signal insert circuit - Google Patents

Abstract

PURPOSE:To make a level of an inserted frame signal stable independently of the level of a video signal by inserting the frame signal from a frame signal level setting means to a video signal whose DC level is recovered by a DC level recovery means. CONSTITUTION:A video signal outputted from a video signal processing means 103 is clamped by a DC level recovery means 106 to recover a DC level. Then a frame signal from a frame signal level setting means 107 through a frame signal insert means 108 is inserted to the video signal whose DC level is recovered by the DC level recovery means 106. Thus, the frame signal is inserted to the video signal after the DC level is recovered. Thus, the DC level of the frame signal is not fluctuated with respect to a reference level of the video signal, the stable frame signal is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a device capable of displaying, on a display screen, a video signal having an aspect ratio different from that of the display screen. The present invention relates to a frame signal insertion circuit used to display a frame signal on a display screen in a display format in which all video signals are displayed.

[Conventional technology]

High-definition television has an aspect ratio of 16:9, which is different from the current NTSC standard.
It is necessary to perform video signal conversion as introduced in Japanese Patent No. 9-70349.

FIGS. 2(a) and (b) show that 4
:1 on a display screen with an aspect ratio of 3.
This figure shows how a video signal having an aspect ratio of 6=9 is displayed.

Figure 2 (a) shows a display format that inserts frame signals at the top and bottom to display all video signals with an aspect ratio of 16:9, and Figure 2 (b) shows a display format that displays all video signals with an aspect ratio of 16:9. This is a display format in which the left and right sides of the signal are cut out and displayed on the display screen at the same time. Further, the display format shown in FIG. 2(a) is also used when displaying cinema-sized or vista-sized video software.

On the other hand, when displaying a video signal with an aspect ratio of 4:3 on a display screen with an aspect ratio of 16:9, frame signals are inserted on the left and right as shown in Figure 2(c). Two display formats have been considered: one in which all video signals having an aspect ratio of 3:3 is displayed, and the other in which the top and bottom are cut off and displayed on the entire display screen as shown in FIG. 2(d).

[Problem to be solved by the invention]

As mentioned above, when displaying a video signal with an aspect ratio different from that of the display screen on a display screen, there are two display formats: one that inserts a frame signal and displays the entire video signal, and the other that displays the entire video signal by inserting a frame signal. There is a display format that cuts out a part of the video signal and displays it all at once on the display screen, but especially when using the former display format, that is, inserting a frame signal and displaying the entire video signal, the following two methods are used: There were two problems: First, when inserting a frame signal and displaying all the video signals, the part where the frame signal is inserted and the part where the video signal is displayed are different on the display.
Since the deterioration of display devices differs from each other, if such a display is continued for a long time, burn-in will occur, and if a video signal is displayed without inserting a frame signal (for example, if the aspect ratio is the same as that of the display screen) There is a problem in that when displaying a video signal that has a certain amount of data, a difference in brightness occurs in the image.

In particular, in the future, 1 systems such as EDTV and high-definition broadcasting will
If receivers for video signals with an aspect ratio of 6:9 become widespread, there will be many opportunities to display the entire video signal by inserting the above-mentioned frame signal. Furthermore, since the mainstream of broadcasting will continue to be based on the current system for some time, it is thought that the time for which the above-mentioned display is performed will be extremely long. Therefore, it is necessary to take fundamental measures to prevent burn-in caused by frame signals.

Conventionally, in order to solve this problem, a method of inserting and displaying another video signal in the part where the frame signal is inserted, or a method of displaying the frame signal by inserting it, or a method of displaying the frame signal, as introduced in Japanese Patent Application Laid-open No. 1-171373, has been proposed. A method has been considered in which the position of the part where the signal is inserted is gradually shifted over time, but in the latter case, for example, when viewed from the user side, the horizontal center moves over time during viewing. This results in an image that looks quite strange, which is problematic.

Second, when displaying all video signals by inserting a frame signal, there is a problem in that the level of the inserted frame signal changes depending on the level of the video signal.

That is, in general, a video signal is subjected to black level correction in a video signal processing circuit where a pedestal level is changed according to the level of the video signal, and then the video signal that has undergone black level correction is fixed at a constant level. A level frame signal is inserted. Then, the video signal into which the frame signal has been inserted is reproduced at a DC level in a clamp circuit. As a result of this DC level reproduction, the pedestal level of the video signal will be aligned, but the level of the inserted frame signal will vary depending on the level of the video signal and will not be constant. It ends up.

The present invention has been made in view of the problems of the prior art described above, and therefore, a first object of the present invention is to provide a display screen with a video signal having an aspect ratio different from that of the display screen. To provide a frame signal insertion circuit capable of stabilizing the level of an inserted frame signal regardless of the level of a video signal when displaying a video signal.

A second object of the present invention is to be able to display a natural image when displaying a video signal having an aspect ratio different from that of the display screen on a display screen, and moreover, to An object of the present invention is to provide a frame signal insertion circuit that can prevent burn-in.

[Means to solve the problem]

In order to achieve the first object among the above-mentioned objects, the present invention inputs an analog video signal, converts the analog video signal into a digital video signal, and displays it on the west side of the display means. a video signal processing means that performs a predetermined conversion on the video signal so that the video signal is not distorted when displayed, and then converts the digital video signal into an analog video signal and outputs the analog video signal, and the video signal processing means DC level reproducing means for reproducing the DC level of the video signal from the
frame signal level setting means for generating a frame signal, setting its level and outputting it; frame signal insertion means for inserting the frame signal from the frame signal level setting means into the video signal from the DC level reproduction means; (hereinafter, this configuration will be referred to as the first configuration).

Moreover, in order to achieve the second object among the above-mentioned objects, the present invention inputs a video signal, reproduces a synchronization signal from the video signal and generates a control signal, and generates the synchronization signal and the control signal. and a video signal that receives an output signal from the synchronization signal processing means and the video signal, and inserts a frame signal into the video signal according to the output signal and outputs the video signal. a processing means, a control means for detecting whether the power is turned on or off and controlling the center adjustment means according to the detection result, and controlling the synchronization signal processing means each time the power is turned on under control by the control means. and center adjustment means for changing the timing of the synchronization signal and control signal output by the synchronization signal processing means (hereinafter, this configuration will be referred to as a second configuration).

In addition, in order to achieve the second purpose, a video signal is input, and in the case of the first signal processing, the video signal is processed so that the video signal is not distorted when displayed on the display screen of the display means. A predetermined first conversion is performed on the video signal, and a frame signal is inserted into the video signal and output, and in the case of second signal processing,
video signal processing means that performs a predetermined second conversion on the video signal and outputs the video signal so that the video signal is not distorted when displayed on the display screen of the display means; and a control means for controlling the video signal processing means according to the detection result (hereinafter, this structure will be referred to as a third structure).

Furthermore, in order to achieve the second objective, a video signal is input, the video signal is converted from a composite signal into a luminance signal and a color difference signal, and when displayed on the display screen of the display means, the video signal is a video signal processing means that performs a predetermined conversion on the video signal so that the signal is not distorted; and inputting the luminance signal obtained by the video signal processing means;
frame signal level setting means for generating a frame signal, setting the level of the frame signal according to the level of the inputted pre-evidence luminance signal, and outputting the frame signal; (hereinafter, this configuration will be referred to as a fourth configuration).

[Effect]

In the first configuration, the input analog video signal is converted into a digital video signal by the video signal processing means, and further, the video signal is not distorted when displayed on the display screen of the display means. , a predetermined conversion is performed, and then the signal is converted into an analog video signal and output. The video signal output from the video signal processing means is clamped by the DC level reproducing means to reproduce the DC level. The frame signal insertion means inserts a frame signal from the frame signal level setting means into the video signal reproduced at the DC level by the DC level reproduction means.

Therefore, by inserting the frame signal into the video signal after the DC level has been reproduced, the DC level of the frame signal will not fluctuate with respect to the reference level of the video signal, and a stable frame signal can be obtained.

Further, in the second configuration, the center adjustment means controls the synchronization signal processing means under the control of the control means every time the power is turned on, and generates a synchronization signal output by the synchronization signal processing means. Change the timing of control signals. Therefore, each time the power is turned on, the center position of the portion where the video signal is displayed changes on the display screen of the display means.

Therefore, the boundary between the part where the frame signal is inserted and the part where the video signal is displayed moves every time the power is turned on.
They will no longer be in the same position, making it difficult to detect burn-in.

Further, in the third configuration, when the first signal processing is performed in the video signal processing means, a frame signal is inserted into the display screen of the display means to display all the video signals. The first display format (see Figure 2 (a) above,
(e)) and the second signal processing is performed, a second display format in which a part of the video signal is cut out and displayed on the display screen all at once. (
The display is performed in the display format shown in FIGS. 2(b) and 2(d) described above. When the power is turned on, the control means controls the video signal processing means to cause the video signal processing means to perform the second signal processing. Therefore, when the power is turned on, the display is performed in the second display format.

According to such a configuration, the time to insert and display the frame signal is short (therefore, it is effective in alleviating burn-in.
As shown in FIGS. 2(b) and 2(d), there is a problem that part of the video signal is cut off, but this has almost no effect on images of boat fishing.

Furthermore, in the fourth configuration, the frame signal level setting means includes a control means, detects the average brightness level of the video signal from the input brightness signal, and detects the average brightness level of the frame signal. is detected, and the level of the frame signal is set under the control of the control means so that both levels are the same.

Therefore, since the level of the set frame signal is the same as the average brightness level of the video signal, the rate of deterioration of the display device in the part where the frame signal is inserted and the part where the video signal is displayed is almost the same. The burn-in is caused by Hitachi.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, 101 is a video signal input terminal that inputs an analog video signal, 102 is an A/D converter that converts the input analog video signal into a digital video signal, and 103 is a video signal that converts the video signal from a composite signal. A video signal processing circuit 104 converts the video signal into a luminance signal and a color difference signal, and also performs conversion so that the video signal is not distorted when displayed on a display screen; 105 is a synchronous signal processing circuit that generates a control signal; 105 is a D/A converter that converts the digital video signal (consisting of a luminance signal and a color difference signal) from the video signal processing circuit 103 into an analog video signal; 106 is a D/A converter that converts the A clamp circuit reproduces a DC level from the analog video signal from the D/A converter 105, and 107 is a frame signal level setting circuit that generates a frame signal consisting of a luminance signal and a color difference signal, sets its level, and outputs it. , 108 converts the video signal from the clamp circuit 106 and the frame signal from the frame signal level setting circuit 107 into the synchronization signal processing circuit 104.
109 is the selection circuit 1 which inserts a frame signal into the video signal and outputs it by switching according to a control signal from the selection circuit 1;
110 is a display for displaying the video signal into which the frame signal from the inverse matrix circuit 109 is inserted, from a luminance signal and a color difference signal to an RGB signal; This is the display screen.

In FIG. 1, it is assumed that the video signal from the video signal input terminal 101 has an aspect ratio of 4:3, such as an NTSC signal, and the display has an aspect ratio of 16:9 as the display screen 110. Assume that you have a screen.

The video signal converted into a digital signal by the A/D converter 102 is converted into a composite signal by filter processing such as Y/C separation in the video signal processing circuit 103 according to a control signal from the synchronization signal processing circuit 104. is converted into a luminance signal and a color difference signal, and further the above-mentioned 16
Video signal conversion is performed to compress the video signal in the horizontal direction so that the video signal is not distorted when displayed on the display screen 110 having an aspect ratio of :9. The video signal output from the video signal processing circuit 103 is converted back to an analog signal by the D/A converter 105, and then reproduced at a DC level by the clamp circuit 106.

In the frame signal level setting circuit 107, the display screen 110
A frame signal is generated to be inserted at both ends of the video signal, and its level is set and output. To set the frame signal level,
Easy analog settings for luminance signals and color difference signals.

The frame signal from the frame signal level setting circuit 107 and the video signal from the clamp circuit 106 are controlled by the control signal from the synchronization signal processing circuit 104, and are switched by the selection circuit 10B.

Furthermore, after being converted into RGB signals by the inverse matrix circuit 109, the display screen 110 of the display is
will be displayed.

When the aspect ratio of the video signal is 4=3 and the aspect ratio of the display screen 110 is 16:9, the display format is such that frame signals are inserted on the left and right sides as shown in FIG. .

In this embodiment, the frame signal is inserted after the video signal is clamped in the clamp circuit 106 and the DC level is determined (that is, after the pedestal level is aligned), so that the frame signal is displayed on the display screen 110 of the display. This has the effect of stabilizing the level of the frame signal without fluctuation.

Furthermore, in this embodiment, the explanation has been made assuming that the aspect ratio of the input video signal is 4:3 and that the display screen 110 of the display to be displayed has an aspect ratio of 16:9. , when the aspect ratio of the input video signal is 16:9 and the aspect ratio of the display screen 110 of the display to be displayed is 4:3, that is, when there are frame signals at the top and bottom as shown in FIG. It can also be applied when inserted.

Next, FIG. 3 is a block diagram showing a second embodiment of the present invention.

In FIG. 3, 301 is a frame signal level setting circuit that generates a frame signal consisting of an ROB signal, sets its level and outputs it, and 302 is a video signal converted into an RGB signal output from the inverse matrix circuit 108. This is a selection circuit that inserts a frame signal into a video signal and outputs the video signal by switching between a frame signal consisting of RGB signals outputted from the frame signal level setting circuit 107 using a control signal from the synchronization signal processing circuit 10. The rest is the same as the embodiment shown in FIG.

In this embodiment, the selection circuit 3 inserts the frame signal into the video signal.
The difference from the embodiment shown in FIG. 1 is that the position of 02 is after the inverse matrix circuit 108.

The advantage of this embodiment is that the level of the frame signal remains stable without fluctuations, similar to the embodiment shown in FIG.

Next, FIG. 4 is a block diagram showing a third embodiment of the present invention.

In FIG. 4, 401 is a center adjustment circuit that changes the timing of the synchronization signal and control signal output from the synchronization signal processing circuit 104, and 402 is a center adjustment circuit that detects whether the power is turned on or off.
a control circuit that controls the center adjustment circuit accordingly;
403 is a clamp circuit 106 similar to the embodiment shown in FIG.
This is a frame signal insertion/inverse matrix circuit consisting of a frame signal level setting circuit 1079 selection circuit 108 and an inverse matrix circuit 109. The rest is the same as the embodiment shown in FIG.

In this embodiment, the control circuit 402 detects whether the power is turned on or off, and controls the center adjustment circuit 402 accordingly.

Under the control of the control circuit 402, the center adjustment circuit 402 adjusts the synchronization signal processing circuit 10 every time the power is turned on.
4 to change the timing of the synchronization signal and control signal output from the synchronization signal processing circuit 104.

As a result, every time the power is turned on, the video signal processing circuit 1
The output timing of the video signal output from 03, the switching timing of the selection circuit in the frame signal insertion/inverse matrix circuit 402, and the display timing on the display screen 110 of the display each change. As a result, each time the power is turned on, the display screen 110
In this case, the position of the horizontal center of the portion where the video signal is displayed shifts to the left or right.

Note that the control circuit 401 can be realized relatively easily by using a microcomputer.

Next, means for changing the output timing of the video signal in the video signal processing circuit 103 will be explained using FIGS. 5 and 6.

FIG. 5 is a block diagram showing an example of an output part of the video signal processing circuit in FIG. 4, and FIG. 6 is a timing chart showing the timing of the main part signals in FIG.

In FIG. 5, 501 is an input terminal for inputting a double-speed video signal (consisting of a luminance signal and a color difference signal); 502
503 has a storage capacity for one horizontal period of the video signal and is used to compress the input video signal in the horizontal direction on the display screen 110; 503 stores the compressed video signal (consisting of a luminance signal and a color difference signal); ), an output terminal that outputs
504 is an input terminal for inputting a write clock (WCK), 505 is an input terminal for manually inputting a read clock (RCK), 506 is an input terminal for inputting a write reset signal (WRES), and 507 is a read reset signal (R
Note that the write clock, read clock, write reset signal, and read reset signal are input to the synchronization signal processing circuit 10.
4 as a control signal.

In FIG. 5, the video signal shown in FIG. 6(a) is input from an input terminal 501, and is written into a line memory 502 in accordance with a write clock input from an input terminal 5.4. The writing timing at this time is input terminal 5.
It is controlled by the write reset signal shown in FIG. 6(b) input from 06.

The video signal written in the line memory 502 is read out from the line memory 502 in accordance with the read clock input from the input terminal 505.

The read timing at this time is controlled by a read reset signal shown in FIG. 6(C) inputted from the input terminal 507.

Therefore, the video signal output from the output terminal 503 has a timing as shown in FIG. 6(d).

Furthermore, if the read reset signal is changed to the timing shown in FIG. 6(C''), the video signal output from the output terminal 503 will have the timing shown in FIG. 6(d').

Note that if the frequency of the read clock is set to be about 473 times the frequency of the write clock, the output video signal can be made distortion-free.

As described above, by changing the timing of the read reset signal output as a control signal from the synchronization signal processing circuit 1.4, the output timing of the video signal can be changed relatively easily, and as a result, As a result, the position of the horizontal center of the portion where the video signal is displayed on the display screen 110 can be shifted.

As explained above, according to this embodiment, when inserting a frame signal into the display screen 110 of the display to display all the video signals, each time the power is turned on, the displayed portion of the video signal is The horizontal center position can be shifted. Therefore, since the position of the boundary between the inserted part of the frame signal and the displayed part of the video signal is not fixed, burn-in caused by the frame signal can be alleviated, and when the video signal is displayed without inserting the frame signal ( For example, when displaying a video signal having an aspect ratio equal to the aspect ratio of the display screen), there is no difference in brightness between images, making it difficult to detect boundaries.

Furthermore, when viewed on the display screen 110 of the display, the horizontal center position of the displayed portion of the video signal appears to shift each time the power is turned on; Since the position of the horizontal center is fixed, the user does not feel any discomfort.

Next, FIG. 7 is a block diagram showing a fourth embodiment of the present invention.

In FIG. 7, 601 is a video signal processing circuit, 602 is a filter processing circuit that converts the video signal from a composite signal into a luminance signal and a color difference signal through filter processing such as Y/C separation and interpolation, and 603 is a 16:9 A video signal conversion circuit 701 performs video signal conversion to compress the video signal in the horizontal direction so that the video signal is not distorted when displayed on the display screen 110 having an aspect ratio of Average level of the brightness signal from the processing circuit 602 (i.e., average brightness level of the video signal)
A frame signal level setting circuit 702 sets and outputs the level according to the frame signal conversion circuit 603 and the frame signal from the frame signal level setting circuit 701 from the synchronization signal processing circuit 104. A selection circuit 703 is a clamp circuit 1 similar to the embodiment shown in FIG.
06 and an inverse matrix circuit 109. The rest is the same as the embodiment shown in FIG.

The feature of this embodiment is that the frame signal is inserted on the digital signal processing side.

The frame signal level setting circuit 701 sets the level of the frame signal to be displayed based on the level of the luminance signal output from the filter processing circuit 602.

FIG. 8 shows a specific example of the frame signal level setting circuit 701.

In FIG. 8, 801 is the filter processing circuit 602.
802 is an input terminal for inputting a gate signal output as a control signal from the synchronization signal processing circuit 104; 803 is an input terminal for inputting a luminance signal from the synchronous signal processing circuit 104;
804 is a low-pass filter; 804 is a low-pass filter; 804 is a low-pass filter;
05 is a limiter that limits the amplitude, and 806 is an output terminal that outputs a frame signal.

In the average brightness level calculation circuit 803, the input terminal 8
The synchronizing signal period is removed by the gate signal from 02, and the average luminance level of only the video period is calculated.

The output signal of the average brightness level calculation circuit 803 is band-limited by a low-pass filter 804, processed to prevent sudden level fluctuations, and then further processed to prevent the frame signal from being extremely high or low in level. In order to avoid this, the limiter 805 limits the amplitude and outputs the signal.

FIG. 9 shows a specific example of the average brightness level calculation circuit 803.

In FIG. 9, 901 is an adder, 902 is a subtracter, 9
03 is a coefficient unit, 904 is a delay circuit, and 9.5 is an output terminal that outputs an average luminance level.

This specific example is a circuit that integrates an input luminance signal, and the tracking characteristics for the input signal are determined by the coefficients of the coefficient multiplier 903. Further, the delay circuit 904 holds the signal for a synchronization signal period in response to a gate signal from the input terminal 802. Therefore, the integration operation is stopped during the synchronization signal period, and the average luminance level of only the video period is output from the output terminal 905. Further, here, the delay circuit 904 does not need to delay each pixel, but may hold and delay several points extracted from the video period. As described above, the frame signal level setting circuit 701 outputs a frame signal whose level follows the average luminance level of the video signal. This frame signal is switched by the selection circuit 702 and output.

According to this embodiment, since the level of the frame signal matches the average brightness level of the video signal, the display screen 11 of the display
0, the rate of deterioration in the portion where the video signal is displayed and the portion where the frame signal is inserted is equal, which is effective in preventing burn-in.

Next, FIG. 10 is a block diagram showing a fifth embodiment of the present invention.

In FIG. 10, 1201 is the filter processing circuit 6
This is a filter circuit that temporally thins out the luminance signal output from 02, but the rest is the same as the embodiment shown in FIG.

In FIG. 10, assuming that the luminance signal from the filter processing circuit 602 has NXMM pixels, the filter circuit 1201 smoothes it by low-pass filter processing and then thins it out to HXyn (n≦N, m5M) pixels. do. Other operations are the same as the embodiment shown in FIG.

In this embodiment as well, since the level of the frame signal matches the average brightness level of the video signal, the display screen 1 of the display
In No. 10, the rate of deterioration in the portion where the video signal is displayed and the portion where the frame signal is inserted is equal, which is effective in preventing burn-in.

Next, a sixth embodiment of the present invention will be described.

This embodiment has almost the same configuration as the embodiment shown in FIG. 7, except that a frame signal level setting circuit shown in FIG. 11 is used instead of the frame signal level setting circuit 701.

FIG. 11 is a block diagram showing a frame signal level setting circuit used in the sixth embodiment of the present invention.

In FIG. 11, 1000 is a frame signal level setting circuit;
1001 is an average value calculation circuit that calculates the average level of the luminance signal input from the input terminal 801; 1002 is a signal holding circuit that holds the output signal from the average value calculation circuit 1001; 1003 is a frame signal setting circuit; 1004 100B is a signal holding circuit that holds the output signal from the frame signal setting circuit 1003; 1005 is a subtracter; 1006 is an average value calculation circuit that calculates the average level of the output signal from the subtracter 1005; 1007 is an adder; is the power on/
The signal holding circuit 1002 is detected to be off, and the signal holding circuit 1002 is
．． 1004. Others are No. 8
This is the same as the specific example in the figure.

In FIG. 11, the signal holding circuit 1002 receives the output signal from the average value calculation circuit 1001, and the signal holding circuit 1004 receives the output signal from the frame signal setting circuit 1003 when the power supply is turned off under the control of the control circuit 1009. Hold when off.

When the power is turned on, the signal held in the signal holding circuit 1002 is output, and the signal held in the signal holding circuit 1002 is outputted to the average value calculation circuit 100.
1 as the initial value.

Furthermore, the signal held in the signal holding circuit 1004 is
It continues to be output as a frame signal until the power is turned off next. Therefore, while the power is on, a signal at a fixed level is always output as a frame signal.

Further, the subtracter 1005 calculates the difference between the level of the currently output frame signal (that is, the output signal of the signal holding circuit 1004) and the level of the output signal from the average value calculation circuit 1001, and outputs the difference. . The average value calculation circuit 1006 calculates the average level of the output signal from the subtracter 1005.

Further, the adder 10QT includes the average value calculation circuit 10
06 and the level of the currently output frame signal (that is, the output signal of the signal holding circuit 1004), and calculates the addition value of the level of the output signal from the frame signal setting circuit 1003.
supply to. As described above, the output signal of the frame signal setting circuit 1003 held by the signal holding circuit 1004 when the power is turned off becomes the next new frame signal.

That is, by correcting the difference between the average level of the luminance signal and the level of the frame signal, a new level of the frame signal is set when the power is turned on next time.

In this embodiment, the level of the frame signal does not change while the power is turned on, and the deviation in the average luminance level between the frame signal and the video signal can be calculated accurately, which eliminates the burn-in problem. It is effective in eliminating.

Next, a seventh embodiment of the present invention will be described.

Similar to the embodiment shown in FIG. 11, this embodiment has almost the same configuration as the embodiment shown in FIG. 7, but the frame signal level setting circuit 70
The difference is that a frame signal level setting circuit shown in FIG. 12 is used instead of the circuit shown in FIG.

FIG. 12 is a block diagram showing a frame signal level setting circuit used in the seventh embodiment of the present invention.

In FIG. 12, 1101 is a subtracter, 1102 is an average value calculation circuit that calculates the average level of the output signal from the subtracter 1101, and 11o3 is a signal holding circuit that holds the output signal from the average value calculation circuit. be. The rest is the same as the embodiment shown in FIG.

In this embodiment, the subtracter 1101 calculates the difference between the level of the current frame signal output from the signal holding circuit 1004 and the level of the luminance signal from the input terminal 801, and outputs the output from the subtracter 1101. The average level of the signal is calculated by the average value calculation circuit 1102. Other operations are similar to those in the embodiment shown in FIG. 11, and the level of the frame signal is set.

In this embodiment as well, the level of the frame signal can be set to a level with less burn-in, and compared to the embodiment shown in FIG. 11, the average level calculation circuit can be reduced to one system and the circuit size can be reduced. be.

Next, FIG. 13 is a block diagram showing an eighth embodiment of the present invention.

In FIG. 13, 1301 is a video signal processing circuit;
02 is a filter processing circuit that converts a video signal from a composite signal into a luminance signal and a color difference signal through filter processing such as Y/C separation and interpolation; 1303 is a video signal conversion circuit that can convert display formats; A control circuit 1304 detects whether the power is turned on or off and controls the video signal conversion circuit 1303 at least when the power is turned on. The rest is the same as the embodiment shown in FIG.

In this embodiment, since the display format can be converted by the video signal conversion circuit 1303, a video signal having an aspect ratio of 4:3 is displayed on the display screen 11O of the display having an aspect ratio of 16:9. In this case, Fig. 2 (c
) can be displayed in the display format shown in Figure 2 (d).
It can also be displayed in the display format.

That is, in the video signal conversion circuit 1303, as shown in FIG.
), the display screen 110
When displaying in the display format shown in FIG. 2(d), the video signal is compressed in the horizontal direction so that it will not be distorted when displayed on the display screen 110. Performs video signal conversion that expands vertically. These conversions can be realized by using field memory or line memory.

In addition, the control circuit 13 determines which display format to display.
04 is determined by controlling the video signal conversion circuit 13o3. That is, the control circuit 1304 detects whether the power is turned on or off, and when the power is turned on, controls the video signal conversion circuit 1303 to display in the display format shown in FIG. 2(d). When this display format is adopted, part of the video signal is cut off and is no longer displayed, but this is hardly a problem in normal software. Furthermore, if the user does not like this display format, he/she can then use the control circuit 1304
It is possible to switch to the display format shown in FIG. 2(C) via .

According to this embodiment, when the power is turned on, the state shown in FIG. 2(d) is always
Because the video signal is displayed in the display format of
Once the amount of burn-in has decreased, if you display a video signal without inserting a frame signal (for example, if you display a video signal with the same aspect ratio as the display screen), the brightness difference will appear in the image. This has the effect of making it difficult to detect boundaries.

Furthermore, in this embodiment, the aspect ratio of the input video signal is 4:3, and the display screen 110 of the display to be displayed has an aspect ratio of 16:9. The aspect ratio of the video signal to be displayed is 16:9, and the display screen 1 of the display to be displayed is
When the aspect ratio of 10 is 4:3, the video signal conversion circuit 1303 can convert the display format, so the display format shown in FIG. 2(a) and the display format shown in FIG. 2(b) are When the power is turned on, the second
The control circuit 1304 causes the display to be displayed in the display format shown in FIG.
may control the video signal conversion circuit 1303.

In addition, as the video signal conversion circuit 1303, the display format shown in FIG. 2(a), the display format shown in FIG. 2(b), and the display format shown in FIG.
A display format that can be converted between the display format shown in FIG. 2(c) and the display format shown in FIG. 2(d) may be used.

〔Effect of the invention〕

As explained above, according to the present invention, when a video signal having an aspect ratio different from that of the display screen is displayed on the display screen of the display of the present invention, the insertion is performed regardless of the level of the video signal. The level of the frame signal can be stabilized.

Further, it is possible to display an image that does not give an unnatural feeling, and moreover, it is possible to prevent burn-in due to frame signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is an explanatory diagram showing how a video signal having an aspect ratio different from that of the display screen is displayed on the display west side of the display. FIG. 3 is a block diagram showing a second embodiment of the present invention. 4 is a block diagram showing a third embodiment of the present invention, FIG. 5 is a block diagram showing a specific example of the output section of the video signal processing circuit in FIG. 4, and FIG. 6 is a block diagram showing the main parts in FIG. 5. A timing chart showing signal timing, FIG. 7 is a block diagram showing a fourth embodiment of the present invention, FIG. 8 is a block diagram showing an example of the frame signal level setting circuit in FIG. 7, and FIG. FIG. 8 is a block diagram showing an example of the average brightness level calculation circuit; FIG. 10 is a block diagram showing a fifth embodiment of the present invention; FIG. 11 is a frame used in the sixth embodiment of the present invention. A block diagram showing a signal level setting circuit, FIG. 12 is a block diagram showing a frame signal level setting circuit used in a seventh embodiment of the present invention, and FIG. 13 is a block diagram showing an eighth embodiment of the present invention. , is. Explanation of symbols 101...Video signal input terminal, 102...A/D converter, 103...Video signal processing circuit, 104...Synchronization signal processing circuit, 105...D/A converter, 106・
... Clamp circuit, 107 ... Frame signal level setting circuit, 10th ... Selection circuit, 109 ... Inverse matrix circuit, 110 ... Display, 301 ... Frame level setting circuit, 302 ... Selection circuit, 401... Center adjustment circuit, 402... Control circuit, 403... Frame signal insertion/inverse matrix circuit, 502... Line memory,
601... Video signal processing circuit, 602... Filter processing circuit, 603... Video signal conversion circuit, 701...
- Frame signal level setting circuit, 702... selection circuit, 70
3... Analog core circuit, 801... Brightness signal input terminal, 802... Gate signal input terminal, 803...
Average brightness level calculation circuit, 804...Low pass filter, 805...Limiter, 806...Frame signal output terminal, 901...Adder, 902...Subtractor, 903
... Coefficient unit, 904 ... Delay circuit, 905 ... Average brightness level output terminal, 1001.1006 ... Average value calculation circuit, 1002°1004 ... Signal holding circuit,
1003...Frame signal setting circuit, 1005...Subtractor, 1007...Adder, 1008...Control circuit, 1
101... Subtractor, 1102... Average value calculation circuit,
1103...Signal holding circuit, 1201...Filter circuit, 1301...Video signal processing circuit, 1302...
- Filter processing circuit, 1303... Video signal conversion circuit, 1304... Control circuit. Agent Patent Attorney Akio Namiki III Figure 112 Figure (C) (d) Figure 5 Figure 3 @ 4 Figure 11i Figure IEa Figure 1110 Figure *1tS

Claims (1)

[Claims] 1. In a device capable of displaying a video signal having an aspect ratio different from that of the display screen on a display screen of a display means, converting an analog video signal into a digital video signal. analog/digital (hereinafter referred to as
converting means (referred to as A/D) and converting the video signal from the A/D converting means from a composite signal into a luminance signal and a color difference signal, and the video signal is not distorted when displayed on the display screen of the display means. a video signal processing means for performing a predetermined conversion on the video signal; and a digital/analog (hereinafter referred to as D/A) conversion means for converting the digital video signal from the video signal processing means into an analog video signal. , a DC level reproducing means for reproducing the DC level of the video signal from the D/A converting means, and a frame signal level setting means for generating a frame signal consisting of a luminance signal and a color difference signal, setting the level thereof, and outputting the frame signal. , frame signal insertion means for inserting the frame signal from the frame signal level setting means into the video signal from the DC level reproduction means; and frame signal insertion means for inserting the frame signal from the frame signal level setting means into the video signal from the DC level reproduction means; Below, R
GB signal), the video signal from the converting means is input to the display means, and the video signal with the frame signal inserted is displayed on the display screen of the display means. A frame signal insertion circuit characterized by: 2. In a device capable of displaying a video signal having an aspect ratio different from that of the display screen on the display screen of the display means, A/D conversion means for converting an analog video signal into a digital video signal. The video signal from the A/D conversion means is converted from a composite signal into a luminance signal and a color difference signal, and a predetermined signal is added to the video signal so that the video signal is not distorted when displayed on the display screen of the display means. a video signal processing means for converting the digital video signal from the video signal processing means into an analog video signal; and a D/A conversion means for converting the digital video signal from the video signal processing means into an analog video signal; DC level reproducing means for reproducing; converting means for converting the video signal from the DC level reproducing means from a luminance signal and a color difference signal into an RGB signal;
Frame signal level setting means for generating a frame signal consisting of RGB signals, setting the level and outputting the frame signal, and frame signal insertion means for inserting the frame signal from the frame signal level setting means into the video signal from the conversion means. A frame characterized in that the video signal from the frame signal insertion means is input to the display means, and the video signal into which the frame signal has been inserted is displayed on the display screen of the display means. Signal insertion circuit. 3. In a device capable of displaying a video signal having an aspect ratio different from that of the display screen on the display screen of the display means, inputting the video signal, reproducing a synchronization signal from the video signal, and controlling the device. synchronization signal processing means for generating a signal and outputting the synchronization signal and the control signal;
video signal processing means that inputs the output signal from the synchronization signal processing means and the video signal, inserts a frame signal into the video signal according to the output signal, and outputs the inserted frame signal;
a control means that detects whether the power is on or off and controls the center adjustment means according to the detection result; and a control means that controls the synchronization signal processing means each time the power is turned on, and performs the synchronization. the center adjustment means for changing the timing of the synchronization signal and control signal output by the signal processing means; inputting the video signal from the video signal processing means to the display means and displaying the display on the display means; A video signal with a frame signal inserted therein is displayed on the screen according to the output signal from the synchronization signal processing means, and each time the power is turned on, on the display screen of the display means,
A frame signal insertion circuit characterized in that the center position of a portion where a video signal is displayed is changed. 4. In a device capable of displaying a video signal having an aspect ratio different from that of the display screen on the display screen of the display means, input the video signal, and in the case of the first signal processing, perform the above-mentioned In order to prevent the video signal from being distorted when displayed on the display screen of the display means, the video signal is subjected to a predetermined first conversion, a frame signal is inserted into the video signal and output, and a second signal processing is performed. In this case, video signal processing means performs a predetermined second conversion on the video signal and outputs the video signal so that the video signal is not distorted when displayed on the display screen of the display means, and detects whether the power is turned on or off. and a control means for controlling the video signal processing means according to at least the detection result, inputting the video signal from the video signal processing means to the display means, and displaying the video signal on the display screen of the display means. , when the first signal processing is performed in the video signal processing means, display is performed in the first display format in which a frame signal is inserted and all the video signals are displayed, and the second
When the signal processing is performed, a part of the video signal is cut out and displayed in the second display format to fill the display screen, and when the power is turned on, the control means controls the video signal. A frame signal insertion circuit characterized in that the circuit controls a processing means to cause the video signal processing means to perform the second signal processing. 5. In a device capable of displaying a video signal having an aspect ratio different from that of the display screen on the display screen of the display means, A/D conversion means for converting an analog video signal into a digital video signal. The video signal from the A/D conversion means is converted from a composite signal into a luminance signal and a color difference signal, and a predetermined signal is added to the video signal so that the video signal is not distorted when displayed on the display screen of the display means. video signal processing means for converting the luminance signal, and a luminance signal obtained by the video signal processing means is input, generates a frame signal, and sets the level of the frame signal according to the level of the input luminance signal. frame signal level setting means for outputting; frame signal insertion means for inserting the frame signal from the frame signal level setting means into the video signal from the video signal processing means; and insertion of the frame signal from the frame signal insertion means. D/A converts digital video signals into analog video signals
It is characterized by comprising at least a converting means, inputting the video signal from the D/A converting means to the display means, and displaying the video signal with the frame signal inserted on the display screen of the display means. Frame signal insertion circuit. 6. The frame signal insertion circuit according to claim 5, further comprising filter means for inputting the luminance signal obtained by the video signal processing means, thinning out the luminance signal in time, and outputting the luminance signal; A frame signal insertion circuit characterized in that the level setting means inputs the luminance signal output from the filter means instead of the luminance signal obtained by the video signal processing means. 7. The frame signal insertion circuit according to claim 5 or 6, wherein the frame signal level setting means calculates an average level of the input luminance signal in a video period, and generates a signal having a level corresponding to the average level. A frame signal insertion circuit comprising an average value calculation means for outputting the frame signal as the frame signal. 8. The frame signal insertion circuit according to claim 5 or 6, wherein the frame signal level setting means calculates an average level of the input luminance signal in a video period, and generates a signal having a level corresponding to the average level. and limiter means that inputs the output signal from the average value calculation means, limits the level of the signal to a predetermined range, and outputs the signal as the frame signal. Frame signal insertion circuit. 9. The frame signal insertion circuit according to claim 5 or 6, wherein the frame signal level setting means inputs and holds an output signal from the frame signal setting means and the output signal from the frame signal setting means, and outputs the held signal. a first signal holding means for outputting as the frame signal; and a first average value calculation for calculating an average level of the input luminance signal in a video period and outputting a signal having a level corresponding to the average level. a second signal holding means for inputting and holding the output signal from the first average value calculation means and outputting the held signal; subtracting means for determining the difference between the level and the level of the output signal from the first signal holding means and outputting a signal having a level corresponding to the difference; and calculating the average level of the output signal from the subtracting means. ,
a second average value calculation means for outputting a signal having a level corresponding to the average level; the level of the output signal from the second average value calculation means; and the level of the output signal from the first signal holding means. an addition means for calculating an addition value of the addition value and outputting a signal having a level corresponding to the addition value to the frame signal setting means, and detecting on/off of the power supply and adjusting the first and second signals accordingly holding means and a first control means for controlling the first average value calculation means, and the first and second signal holding means are each controlled by the first control means when the power source is When off, the first average value calculation means holds the input signal and the first average value calculation means
Under the control of the control means, when the power is turned on, the first
A frame signal insertion circuit characterized in that the output signal from the signal holding means is set as an initial value. 10. The frame signal insertion circuit according to claim 5 or 6, wherein the frame signal level setting means comprises a frame signal setting means;
a first signal holding means for inputting and holding an output signal from the frame signal setting means and outputting the held signal as the frame signal;
subtracting means for calculating the difference between the level of the output signal from the signal holding means and outputting a signal having a level corresponding to the difference; and calculating the average level of the output signal from the subtracting means during the video period, an average value calculation means for outputting a signal having a level corresponding to the average level; a second signal holding means for inputting and holding the output signal from the average value calculation means and outputting the held signal; Determining the added value of the level of the output signal from the average value calculation means and the level of the output signal from the first signal holding means, and outputting a signal having a level corresponding to the added value to the frame signal setting means. an addition means; and a first control means for detecting power on/off and controlling the first and second signal holding means and the average value calculation means accordingly;
The and second signal holding means each hold the input signal when the power is turned off under the control of the first control means, and the average value calculation means holds the input signal when the power is turned off under the control of the first control means. A frame signal insertion circuit characterized in that when turned on, the output signal from the first signal holding means is set as an initial value. 11. The frame signal insertion circuit according to claim 5, 6, 7, 8, 9 or 10, which receives the video signal, reproduces a synchronization signal from the video signal, and generates a control signal;
a synchronization signal processing means for outputting the synchronization signal and the control signal and controlling the video signal processing means, the frame signal insertion means, and the display means according to the synchronization signal and/or the control signal; and a second control means for detecting and controlling the center adjustment means according to the detection result, and under the control by the second control means, every time the power is turned on, the synchronization signal processing means is controlled to perform the synchronization. and the center adjustment means for changing the timing of the synchronization signal and control signal output by the signal processing means, and each time the power is turned on, the center position of the part where the video signal is displayed is adjusted on the display screen of the display means. A frame signal insertion circuit characterized in that the frame signal insertion circuit changes. 12. In the frame signal insertion circuit according to claim 5, 6, 7, 8, 9, 10 or 11, instead of the video signal processing means, the video signal from the A/D conversion means is converted from a composite signal. Along with converting into luminance signal and color difference signal,
An image in which either a predetermined first conversion or a predetermined second conversion is selectively applied to the video signal so that the video signal is not distorted when displayed on a display screen of the display means. A signal processing means is provided, and a third control means is provided for controlling the selection operation and the operation of the frame signal level setting means in the video signal processing means, and the third control means controls the video signal processing means. When the first conversion is selected and the frame signal level setting means is operated, the display screen of the display means is changed to a first display format in which a frame signal is inserted and all the video signals are displayed. is displayed, and when the processing means selects the second conversion and the operation of the frame signal level setting means is stopped, a part of the video signal is cut out on the display screen of the display means. A frame signal insertion circuit characterized in that display is performed in a second display format in which the frame signal is displayed to fill the display screen. 13. In the frame signal insertion circuit according to claim 12, the third control means is capable of detecting whether the power is turned on or off, and when the power is turned on, the third control means is capable of detecting whether the power is turned on or off. A display is made in the second display format on the display screen of the display means by causing the processing means to select the second conversion and stopping the operation of the frame signal level setting means. Frame signal insertion circuit.