JPH0442709B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application of the Invention) The present invention relates to a method of processing high-density images processed by an image processing device or a layout scanner for printing plate making.

(Prior art) Recently, as a color plate making device, a computer-based image processing device is used to perform image processing on each of a plurality of original drawings and assemble them (referred to as a collection).
As a result, layout scanner systems (also referred to as total scanner systems) that create one-page layouts are emerging.

In conventional layout scanner systems, some kind of image processing (e.g. rotation, scaling, transformation) on the pixels of the high-density image obtained by the scanner is performed during the operator's operation stage so that the image can be displayed on the monitor. Is it possible to divide a fixed two-dimensional shape into parts according to the capacity of the buffer memory and repeatedly process the divided images for each minute according to the capacity of the buffer memory?
Alternatively, display an image compressed by thinning out the pixels of a high-density image or averaging multiple pixels using a color monitor, and add the required information to the displayed image as necessary. After image processing is performed, the image is processed again using a computer at the fine pixel level of an actual high-density image based on the contents operated by the operator via the monitor.

Then, regarding the image as a result of image processing,
Highly accurate page prints are produced by performing the necessary compilation on the entire page.

However, in the above image processing, rotation, deformation,
When changing the magnification, etc., it takes a lot of time.

(Problems to be Solved by the Present Invention) An object of the present invention is to provide a processing method based on the above premise, even when performing affine transformation processing such as rotation, transformation, and scaling on an actual high-density pixel image. The purpose is to provide a method that can save time.

In other words, the conventional buffer memory for image processing is
Because it has a fixed two-dimensional shape, buffer memory cannot be used efficiently when one image is divided into several parts and processed repeatedly, and images that are larger than the memory capacity are simply divided. This solves the drawback that when rotation or the like is performed, the effective image area becomes extremely small in some cases.

(Technical means for solving the problems) In order to solve the above problems, the present invention is configured as follows.

The image data stored in the input disk memory is divided into a plurality of parts, the image data for each divided part is read out and written to a first buffer memory, and the image data in the first buffer memory is subjected to affine transformation including rotation. , an image processing method in which image data after affine conversion is transferred to a second buffer memory, and the image data in the second buffer memory is read out and stored in an output disk memory, each of the first and second buffer memories being As a two-dimensional array, the X address length and Y address length are variable under the condition of (X+Y=constant), a plurality of address bit modes defining the X address length and Y address length are set in advance, and the first address bit mode is set in advance. , and the second buffer memory, the address bit mode is sequentially selected, and the X in the selected address bit mode is set.
A two-dimensional array rectangle determined by the address length and Y address length is set, and for each address bit mode, an overlapping polygon is found between the rectangle of the first buffer memory subjected to affine transformation and the rectangle of the second buffer memory. , specify the address bit modes of the first and second buffer memories when the area of this overlapping polygon is maximum, and calculate the X address length and Y address length in these specified address bit modes as the first and second buffer memories. Apply to each of the second buffer memories, find a rectangle with the largest area inscribed in the overlapping polygon with the largest area, and use this inscribed rectangle as the output division size corresponding to the second buffer memory; Find the rectangle that encloses the polygon when the enclosing rectangle is inversely transformed, and use this enclosing rectangle as the first
An image processing method characterized in that the input division size corresponds to the buffer memory of.

(Embodiment) FIG. 1 is a basic configuration diagram of a layout scanner system mainly including an image processing device to which the present invention is applied.

The input disk memory (1) stores high-density image data scanned by a color scanner (not shown).

The image read from the input disk memory (1) is transferred to the first memory 4 via the interface (2).
The data is stored in the first buffer memory 4 (hereinafter simply referred to as the first memory 4) according to the address of the first memory 4 by conventional means.

When displaying a stored image, the image read out from the first memory 4 at the video frequency is sent to the display control circuit 5 and displayed on the color monitor 6.
displayed as an image.

Depending on the case, the display may be read simultaneously with the contents of the second buffer memory 10 (hereinafter referred to as the second memory 10), and the contents of the control memory 15 may be read out at the same time as the contents of the control memory 15 for composite display or mask control. is used and displayed.

Although these displays are not shown in the drawings, they are common technical means and are not related to the essence of the present invention, so their explanations will be omitted.

The two-dimensional shape of the first memory 4 and other memories used for displaying is made to match the display screen. In the description here, a square is used. In addition, in the memory usage method described later, 2
This is done without using a mode that changes the shape dimensionally.

Furthermore, the description will be made on the assumption that a generally usable memory size has a capacity of 1024×1024 pixels.

On the other hand, the pixel size of an image separated and sampled by a color scanner used for printing is generally about 50 μm, and even a 10 cm square picture has 2000 x 2000 pixels, so the entire image can be stored in memory. It is normal that you cannot remember everything. Therefore, such a common case will be explained here as well.

For this reason, the interface 2 thins out the image or averages multiple pieces of pixel data.
It has a function of compressing it into one pixel data, and makes the entire image visible on a color monitor. However, the final arithmetic processing on the image cannot be performed on such a thinned out or compressed image;
need to be processed.

Therefore, it may be necessary to divide the image and process it repeatedly. Examples of the present invention regarding this method will be described later.

Referring to FIG. 1, the operation of the entire layout scanner system will be further explained.

The image data stored in the first memory 4 is subjected to image processing as necessary.

The image data in the first memory 4 is sequentially read out and sent to the arithmetic circuit 7 via the data I/O register 3.
After the necessary processing is performed, the data is transferred to the second memory 10 via the data I/O register 11.
is written to.

Data is sequentially transferred for all memory areas, and processing is completed.

The arithmetic circuit 7 has a configuration as shown in FIG. 2, for example.

In FIG. 2, data input from an input data line 24 is operated on by an arithmetic circuit 7. As shown in FIG. For example, when changing the gradation, a lookup table is generally used, and data required by the CPU 16 is stored in the lookup table 19. Then, as the calculation mode, the CPU
16 outputs a command to open buffer 21. At this time, other buffers 20 and 22
is disabled and does not pass data.

The operation mode is sent as a code of several bits and is decoded by decoder 23 to enable the necessary buffers.

The image data then enters the lookup table 19 through the input data line 24, undergoes any necessary processing, and is output from the buffer 21 to the output data line 25. These arithmetic circuits are
Perform pipeline operation.

The buffer 20 is enabled in the pass mode in which no calculations are performed. This pass mode is used, for example, when a certain portion of data in the first memory 4 is to be stored in the second memory 10 in an affine conversion process.

A circuit 26 for performing other calculations is provided, but these can be added as necessary. Corresponding buffers 22 and the like are added in accordance with these additions.

The results calculated in this way are stored in the second memory 10.

By displaying the contents of the first memory 4 on the monitor 6 and the contents of the second memory 10 on the monitor 6, the state before and after processing can be seen.

If you want to process only a specific area, mask data of 1 bit "0" or "1" is stored in advance in the control memory 15 by the CPU 16, and the mask data is stored in the control memory 15 from the first memory 4 and the control memory 15. , the data is simultaneously read out and processed by the arithmetic circuit. For example, when the data from the control memory 15 is "1", the data is read out via the lookup table 19 and the buffer 21 or the arithmetic circuit 26 and the buffer 22 for arithmetic processing. When is "0", it is also possible to perform control such as sending the data to the second memory 10 and storing it via the buffer 20 without performing arithmetic processing using the pass mode.

At this time, data from the control memory 15 is sent to the decoder 23 of the arithmetic circuit 7 via the data I/O register 14 together with other arithmetic modes.

The data to the control memory 15 is transferred to the CPU
16, but CPU16 is
In accordance with commands and coordinate values input by the operator from the tablet 17 or keyboard 18, for example, a circle is created, the inside of the circle is filled in, and data is created in the control memory 15, with the outside being "0" and the inside being "1". . At this time, the operator can obtain the desired coordinates by displaying a cursor or the like corresponding to the memory area on the color monitor 6.

The control memory 15 is also used for arranging a plurality of images on a page, which is one of the main functions of the layout scanner, that is, for collection.

The collection method also uses the same control memory as described above, and uses the contours created by the operator in advance on the CPU 16.
For example, the image from the first memory 4 is transferred to only the "1" part of the control memory 15 onto the second memory 10, various images and contours are repeatedly processed, and the image is transferred onto the second memory 10. Create a page with a collection of images.

The second memory 10 is used as described above, or when combining two images, the second memory 10 is used as a
Two images are stored from the input disk 1 onto the second memory 10 via the interface 2, the data I/O register 3, the pass mode of the arithmetic circuit 7, and the data I/O register 11.

Next, a necessary part of another image is written from the first memory 4 to the second memory 10 using the control memory 15, and the two images are combined.

Furthermore, the processing results on the second memory 10 are stored on the output disk 13. At this time, data is transferred from the second memory 10 to the data I/O register 11.
The data enters the interface 12 via the interface 12 and is stored in the output disk memory 13. The final result of this output disk is output to a color scanner (not shown) and used as an original film for printing.

The address generation circuit 9 is connected to the first memory 4, the second memory
The addresses of the memory 10 and control memory 15 are generated.

When using a memory element with a slow access time, in order to correspond to the video frequency, reading from the memory is performed in parallel and then converted into serial image data for use. Therefore, the memory address is different from that in the above process, but this is a general technical means and will not be described here.

The address generation circuit portion related to the present invention will be described later.

The affine conversion circuit 8 is used to perform affine conversion processing on the address generated by the address generation circuit 9, and the address after affine conversion is provided to the first memory 4. This means that
When performing affine transformation on the image in the first memory 4, the address on the second memory 10 after conversion is generated, the inverse affine transformation is performed, the address on the first memory 4 is obtained, and the image data is is read out and transferred onto the second memory 10.

Next, an outline of the conversion process according to the present invention will be described.

FIG. 3 shows that the size of a certain image 27 is larger than the size of 1024×1024 pixels of the first memory 4 and second memory 10 used in the example.

This image 27 is rotated by a certain angle θ,
A case in which processing for obtaining the image 28 is performed will be described.

When attempting to create a rotated image on the second memory 10 using a conventional method, the following method is used.

First, the image 27 of the size shown in _FIG . Next, the second
generates an address in the memory 10, performs inverse affine conversion on that address, reads data as an address on the first memory 4, and reads the data as an address on the second memory 4.
It is stored in the memory 10 of.

In this way, when all the addresses of the area on the second memory are generated and the corresponding data from the first memory (4) is transferred onto the second memory 10, the area shown in FIG. An image 30 can be stored on the second memory 10.

Next, it is necessary to create a partial image 31, but since this portion is the rotation result of the I ₂ portion of the image 27, the I ₂ portion is read from the input disk memory 1 onto the first memory 4, and the 1 memory 4.

After that, the partial image 31 is stored in the second memory 10.
Address generation is performed in correspondence with the above, inverse affine transformation is performed, the corresponding portion on the first memory 4 is read out, and the corresponding portion is stored on the second memory 10.

In this way, first, partial images 30 and 31 corresponding to the _I5 portion are created on the second memory 10.

This data is stored from the second memory 10 to the output disk 13 via the data I/O register 11 and the interface 12.

Next, the process is repeated in the same manner as above to create partial images 33, 32, and 34, and then partial image 3.
5, 36, and partial images 37, 38, 3
9, 40, then partial image 41, then partial image 4
3. Finally, by creating the partial image 42, the rotated image 28 is completed.

Because of the reversal of the above processing, the image 27 is divided into four parts, and the rotated image 28 is also divided into fourteen parts.

Therefore, the number of data transfers from the input disk memory 1 and the data transfer to the output disk memory 13 becomes very large, and the processing time becomes very long.

The present invention attempts to solve this problem by the method described below.

(1) The XY address lengths of the first memory 4, the second memory 10, and, if necessary, the control memory 15 are made variable. That is, X=Y, X=2Y,
It can be used as a two-dimensional shape ranging from a square to a rectangle, such as 2X=Y. This is hereinafter referred to as address bit mode.

(2) Find the area with the highest processing efficiency when processing images in the various rectangular memory states described in (1). That is, it is determined which rectangular memory shape should be used to handle a larger portion of the image in one process.

(3) Perform actual processing using the results obtained in (2) and the rotation parameters. At this time, the processing time can be shortened by using a method that minimizes image division.

The address generation circuit 9 shown in FIG. 1 is for achieving the above purpose, and FIG. 4 shows an embodiment thereof.

Figure 4A shows a device that makes the X address length and Y address length of a rectangular memory of two-dimensional arrays X and Y variable.Specifically, from the address line of (X+Y)=20 bits, the middle of the bit is set as the upper part. This is an embodiment in which the X and Y address lengths are made variable by dividing into lower parts and sliding the middle part up and down.

Address bit mode 1-5 in this example
is preset as follows.

However, (X+Y)=20 bits.

Mode 1: X=8bit, Y=12bit Mode 2: X=9bit, Y=11bit Mode 3: X=10bit, Y=10bit Mode 4: X=11bit, Y=9bit Mode 5 When X=12bit, Y=8bit In FIG. 4A, the counter ⁴⁴ counts the input timing clock in binary,
2 Outputs the 20-bit address indicated by ¹⁹ .

The lower order bits ²⁰ to ²⁷ of the output of _{the counter 44 are output as the lower order X0 to X7 of} the X address in any of the above address bit modes. Moreover, the upper ²⁸ to ²¹⁹ enter the shift circuit 45, respectively.
The addresses are divided into X addresses and Y addresses by sliding up and down according to the preselected address bit mode.

The configuration of one of each shift circuit 45 is shown in FIG. 4B. In the figure, the decoder 46 enables any one of the buffers 47-1 _{to 47-5} according to the applied 3-bit address bit mode.
The output of the decoder 46 for address bit mode is "1" in only one digit as follows.
stands.

Mode 1: 1,0,0,0,0 from the left Mode 2: 0,1,0,0,0 from the left Mode 3: 0,0,1,0,0 from the left Mode 4 0, 0, 0, 1, 0 from the left when mode 5 is 0, 0, 0, 0, 1 from the left according to the output of this decoder 46.
Any one of _{−1 to 5} is enabled. For example, when address bit mode is 1, buffer 4
7 _-1 only is enabled. Batsuhua 47 _-1～5
Depending on which one of the outputs is enabled, the shift circuits 45-1 _{to 45-16} may shift the upper output of the counter 44.
Distribute 2 ⁸ to 2 ¹⁹ to each address of X and Y.

For example, in address bit mode 1,
As mentioned above, only the buffer 47 _-1 is enabled, so the outputs of the shift circuits 45 _{-1 to 45 -4} are 0 (X ₈ =
X ₉ =X ₁₀ =0), and eventually the lower ²⁰ to ²⁷ outputs of the counter 44 become the X addresses _X0 to _X7 .
At this time, the shift circuit _45-5 outputs the output ²⁹ of the counter 44, and the remaining shift circuits 45-7 _{to 16} ^output the output ^210/219 of the counter 44. 2 ⁸ ~ 2 ¹⁹ is Y address Y ₀ ~
Y becomes ₁₁ .

In addition, in the case of address bit mode 2, only the buffer _47-2 of the shift circuit 45 is enabled, so the outputs of the shift circuits 45-1 _{to 45-3} become 0, and the shift circuit _45-4 outputs the output 2 of the counter 44. ⁸ , and in the end, the lower ²⁰ to ²⁸ of the output of the counter 44
becomes the X address. At this time, since only the buffer _47-2 is enabled as described above, the shift circuits 45-5 _{to 15} are the upper two ⁹ outputs of the counter 44.
~2 ¹⁹ is output, and the Y address is Y ₀ ~Y ₁₁ after all. Note that the output of the shift circuit _45-16 is 0.

The distribution of the X and Y addresses in the case of address bit modes 3 to 5 is the same as described above, so a description thereof will be omitted.

This address output enters the affine conversion circuit 8 and becomes the address of the first memory 4. Also, the address directly becomes the address of the second memory 10 or the control memory 15. Of course, the addresses to the second memory 10 and control memory 15 at this time are:
2 ⁰ to 2 ¹⁹ are given directly.

The affine transformation circuit 8 actually performs an inverse affine transformation. That is, conversion is performed to obtain the address (x, y) on the first memory 4 before rotation that corresponds to the address (X, Y) on the second memory 10 after rotation.

This general formula is (x y)=(ad cd)(x y)+(e f), and an example of its circuit is shown in FIG. This calculation can be done by simply executing the above formula, and the multipliers 48 _{-1 to 4} multiply X and Y by the coefficients a, b, c, and d, and then The term and Y term are added by calculators 49 _-1 and 49 _-2 , and addition with coefficients e and f is performed by adders 49 _-3 and 49 _-4 , and the desired results x and y are output. .

As a result, the original image to be transferred to the coordinates on the second memory 10 after image rotation, that is, the coordinates on the first memory 4, are determined, and the data of the coordinates are transferred to the coordinates on the second memory 10.
from the second memory 4 to the second memory 10.

Next, a specific example of the method according to the present invention will be described.

To summarize the present invention again, the two-dimensional shape of the memory is made variable in multiple types as hardware, and when the capacity of the image is larger than the memory capacity, or even if the capacity is equivalent, the memory capacity is increased due to affine conversion processing. If there is a shortage, the image is divided and processed, and this division method is used to select the optimal state of the two-dimensional shape of the memory and perform image division most effectively, thereby shortening the processing time. .

FIG. 6 is a flowchart illustrating the entire process.

FIG. 7 is a diagram explaining the flowchart of FIG. 6.

First, as a premise, the memory rectangle and the image are always superimposed so that their symmetry centers coincide.

Referring to FIG. 6, the entire processing method according to the present invention will first be described.

Steps . . . in FIG. 6 are the process of finding the optimum address bit mode. That is, through these steps, the address bit mode that maximizes the output image area is determined.

In this step, an inscribed rectangle (a rectangle with sides parallel to the X and Y axes) is determined within the output image area figure obtained in the address bit mode determined above. The area within this rectangle is a single processing unit, and is performed in order to access the disk memory at high speed and to simplify image division.

Steps , , , are steps in which actual image processing is performed. These details will be explained below.

Steps , , , , are executed by a computer program. teeth,
Process using hardware circuits.

An outline of a specific calculation method will be explained using FIG. 7.

7 to 7 show the state in which the input image 27 shown in FIG. 7 is being processed.

Regarding the process shown in FIG. 6, the case where the input image is larger than the memory size as shown in FIG. 7 is considered. Therefore, in the process, the size of the overlapping polygon P is the same as the size of the first memory 4, and in this example, there is no change in the size of the polygon P in the process shown in Figures 1 and 2. , In such a case, the process of can be omitted. As an initial condition when the input image is larger than the memory size, the address bit mode of the first memory 4 is set to 1, for example.
shall be.

First, in this example, the overlapping polygon (P) is the first
It shows the size itself written in the memory 4 of. The relationship between the input image 27 and the first memory 4 is
In the case of FIG. 81 and FIG. 82, the overlapping polygon P is the intersection of the four straight lines of the outline of the image to be processed and the memory when they are overlapped with their centers aligned, It can be calculated by solving a simple linear equation.

In the case of an input image having a complicated shape as shown in FIG. 8 and 3, similar calculations are performed by determining an input image for processing that encloses the entire image in a rectangle.

In FIG. 6, a polygon (Q) is obtained by rotating the overlapping polygon obtained in . This can be done by performing affine transformation of the coordinates of each vertex of the polygon (P) (FIG. 7-).

Now, an overlapping polygon (R) between the polygon (Q) obtained in and the second memory 10 for output image is obtained (FIG. 7-).

Here, the vertex P _i (X _i , Y _i ) of the polygon P is a symmetric point with respect to the polygon P, where the lengths of X and Y of the memory according to the address bit mode (j) are X _j and Y _j . When is rotated by an angle of θ at the center of the memory (X _j /2, Y _j /2), the coordinates of the vertex Q _i of the rotated polygon Q can be determined by the following equation using the affine transformation formula.

Q _i (each vertex) = A * P _i + B A = (COSθ Sinθ - Sinθ COSθ) B = (1/2X _j (1-COSθ) + 1/2Y _j Sinθ, 1/2Y _j (1-COSθ) -1 /2X _j Sin θ) R _i of the overlapping figure of the polygon Q and the second memory 10 for output images can be found by finding the intersection of straight line segments. In general, line segment Pn, Pn ₊₁ and line segment Qn,
The intersection point Rn with Qn ₊₁ is obtained as follows.

Pi = (pxi, pyi) Qi=(qxi, qyi) pj＝pji′−pji qj＝qji′−qji Let rj=qji−pji.

However, i'=i+1, j=x, y.

For the line segment ₊₁ , y=py/px(x-pxn)+pyn For the line segment, ₊₁ , y=qy/qx(x-qxn)+qyn In this case, if we set t=qyrx-qxry/pxqy-pyqx, (However, 0≦t≦1) The intersection point Rn is Rn (x, y) = (pxn + px't, pyn + py't).

Therefore, when the vertices of the n-gon P are P _i and the vertices of the m-gon Q are Q _i , the vertices of the R polygon formed by P and Q are those inside Q among P _i . The part of _i that is inside P is obtained at the intersection of _{i i+1} and _{j j+1} .

Through this calculation, polygon R is obtained. Furthermore, the area of this polygon R is determined. To calculate the area, use Heron's formula to draw line segments from the center of the polygon to each vertex, divide it into triangles, and find the sum of each triangle.

Next, by changing the address bit mode of the second memory 10 for output images, find the address bit mode that is optimal (R is maximum) for the second memory 10 for output images that has the largest polygon R. .

By repeating ~, the first memory for input image 4
For each address bit mode of
Find the largest one for the input image at that time.
Obtain the optimum address bit mode of memory 4.

In this way, the optimum address bit modes for the first memory and the second memory are determined. Note that if the area of the polygon (R) that is the overlapped portion of the rotated polygon (Q) and the second memory 10 is maximum, then
Since the widest part of the image can be handled in one data process, the address bit mode at this time is selected as optimal.

Since the maximum R has been determined, an effective inscribed rectangle s to be actually processed within the polygon is determined.
This effective inscribed rectangle s is set so that when an output image is created on the second memory 10, it can be transferred directly to the output disk 13 as it is, and also to simplify image division and processing.

FIG. 7 shows the effective inscribed rectangle S obtained through the above process, and FIG. 7 is a conceptual diagram showing the size of the rectangle S used for dividing the output image.

FIG. 7 is a conceptual diagram showing the output image and division state on the output disk memory 13,
The solid line shows the output image after rotation processing.
What is shown by the dotted line is the divided state. Figure 7 x is
It is a conceptual diagram showing an input image and a divided state on the input disk memory 1, where the solid line indicates the input image, and the two-dot chain line indicates the divided state. Note that in FIG. 7x, the division state on the output image is indicated by dotted lines for reference.

The effective inscribed rectangle s is determined as described below with reference to the example shown in FIG.

Consider setting the coordinate center to the center of s. First, if there is a part of the overlapping polygon R as shown in Figure 9 in the first quadrant, let the points where its sides intersect with the X and Y axes be T ₃ and T ₁ , and further define the vertex at T ₂ . Suppose you have one. T ₅ is the intersection of the extension line of _{1 2} with the X axis. T ₄ is the coordinate origin.

When each coordinate is taken as shown in the figure, it is assumed that there is a rectangular vertex U ₀ on _{i i+1} (here _{1 2} ).

At this time, the area of the rectangle S(u) is S(u)=X _u *Y _u , and when u moves on _{i i+1} , the maximum u position of S(u) (U ₀ ) is U ₀ :
(t ₁ /2, t ₅ /2) appears.

If U ₀ does not exist on _{i i+1} , choose the point closer to U ₀ between T _i and T _i+1 .

The above is performed for all _{i i+1} to find the U ₀ coordinate that gives the maximum S(u). In this way, the division size s (that is, the effective inscribed rectangle in the overlapping portion of the first memory and the second memory) that allows the image to be processed with the maximum area is determined.

In this state, an example of division in the output image is shown below.
Figure 7-.

Next, in Fig. 6, this inscribed effective rectangle (s)
Consider on the input image. For this purpose, s may be subjected to inverse affine transformation. This state was shown by
FIG.

Next, as in , consider a rectangle (s') surrounded by sides parallel to the XY axes on the input image. This is also necessary for reading input images from the input disk 1 and for simplifying processing.
However, this time, we will find the circumscribed rectangle (s′). This is because, since this is an input image, all images of the reversely affixed portion are required. This state is shown in FIG. 7 xi.

This circumscribing rectangle (s') can be easily determined by using the maximum and minimum values of the coordinates of each vertex, although it corresponds to the inversely affixed output division size (s).

The area of s' thus determined is naturally the size of the optimum address bit mode of the first memory 4. Therefore, we will now find the coordinates of each of the dividing rectangles'.

In this way, the input image first memory 4 in the process when the rotation θ is applied to the input image 27
The optimum address bit mode of the second memory 10 for output images is determined.

The flowchart in FIG. 6 is a procedure for actually processing this using hardware. FIG. 7 xii shows the concept of the first memory and the second memory.

In FIG. 1, the calculations shown in FIGS. 6, 7, and 9 are performed by the CPU 16, and the optimum address bit mode is given to the address generation circuit 9 as data.

Although not shown in the drawings, the CPU 16 controls the DISC in a general manner, such as addressing the reading position of the divided images from the input disk 1 and the output disk 13, and addressing the writing position of the image.

Furthermore, the affine parameters (Fig. 5 a, b,
c, d, e, f) are similarly passed from the CPU 16 to the affine conversion circuit 8.

After the data is set in this way, the effective rectangle (s') obtained by dividing the input image is stored in the first memory 4.
is stored from the input disk 1.

Next, the address generation circuit 9 operates and sequentially outputs addresses to the second memory 10 starting from the first address of the second memory 10.

At this time, at the same time, the address enters the affine conversion circuit 8 in which the inverse affine parameter is set according to the rotation conditions, outputs the corresponding address on the first memory 4, and converts the address from the first memory 4. The data is transferred to the second memory 10.

When one division is completed, the contents of the second memory 10 are stored on the output disk 13, and then a new division of the next input image is processed in the same way. This process is repeated for the number of divisions.

Naturally, since the image passes through the arithmetic circuit 7 during transfer from the first memory 4 to the second memory 10, it is possible to perform other image operations in addition to rotation processing. It is also possible to use the control memory 15 to perform image calculations only on a part of the image.

From this, further, one image is stored on the second memory 10, rotated from the first memory 4, and transferred onto the second memory 10 according to the mask of the control memory 15. It is also possible to synthesize part of the image onto the second memory. That is, image collection - layout processing - is also possible at the same time as rotation.

Even if other affine transformations, such as enlargement and reduction, are performed on the image at the same time, the generality of the affine transformation is not lost, so it can be performed in a single process.

Above, we have explained image processing for each pixel, but even if arithmetic processing, rotation, aggregation (layout), etc. are performed on a coarse image such as thinning, the actual image Each data can be obtained using the above calculations by simply processing the density as it is.

In other words, the rotation, image arrangement, and gradation conversion using a lookup table performed on a rough image are coordinate values and values written to a table, and each pixel is
This is because calculations can be made with an accuracy corresponding to This requirement is very useful for actual layout scanners, and the method of the present invention can be effectively used for these as well.

(Effect of the invention) In this way, by using a variable address length memory in an image processing device, and using a control/calculation means such as a CPU,
The optimum address bit mode is found and the number of repeated processing is minimized.

By performing image division, a highly efficient method with fewer disk accesses can be obtained for processing such as rotation.

[Brief explanation of drawings]

Figure 1 is a basic configuration diagram of a layout scanner according to the present invention, Figure 2 is an example diagram of an arithmetic circuit, Figure 3 is a diagram showing image size, and Figure 4 is an address generation diagram. FIG. 5 is an example diagram of the affine conversion circuit, FIG. 6 is a processing flowchart of the present invention, FIG. 7 is an explanatory diagram of the flowchart, and FIG. 8 is an illustration of the input image and FIG. 9, which is a diagram showing the size of the first memory, is a diagram illustrating how to find the maximum area (S). 1...Input disk memory, 2...Interface, 3...Data I/O register, 4...First
memory (first buffer memory), 5... display control circuit, 6... color monitor, 7... arithmetic circuit, 8... affine conversion circuit, 9... address generation circuit, 10... second memory ( second buffer memory), 11...data I/O register, 13
...Output disk memory, 15...Control memory, 16...CPU, 17...Tablet,
18... Keyboard, 19... Lookup table, 20... Buffer, 21... Buffer, 2
2... Buffer, 23... Decoder, 24... Input data line, 25... Output data line, 2
6...Circuit for performing other calculations, 27...An image input image, 28...An image rotated by θ, 30
~42...partial image, 44...counter, 45...
...Shift circuit, 46...Decoder, 47...Buffer, 48...Multiplier, 49...Adder.

Claims (1)

[Claims] 1. Divide the image data stored in the input disk memory into a plurality of parts, read out the image data for each divided part and write it in a first buffer memory, and write the image data in the first buffer memory to the image data in the first buffer memory. In the image processing method, the image processing method performs an affine transformation including rotation, transfers the image data after the affine transformation to a second buffer memory, reads out the image data from the second buffer memory, and stores it in an output disk memory, the method comprising: Each of the second buffer memories is made into a two-dimensional array, and its X address length and Y address length are made variable under the condition (X+Y=constant), and the address bit mode that defines the X address length and Y address length is set in advance. setting a plurality of address bit modes, sequentially selecting the address bit mode for each of the first and second buffer memories, and setting X in the selected address bit mode.
A two-dimensional array rectangle determined by the address length and Y address length is set, and for each address bit mode, an overlapping polygon is found between the rectangle of the first buffer memory subjected to affine transformation and the rectangle of the second buffer memory. , specify the address bit modes of the first and second buffer memories when the area of this overlapping polygon is maximum, and calculate the X address length and Y address length in these specified address bit modes as the first and second buffer memories. Apply to each of the second buffer memories, find a rectangle with the largest area inscribed in the overlapping polygon with the largest area, and use this inscribed rectangle as the output division size corresponding to the second buffer memory; Find the rectangle that circumscribes the polygon when the enclosing rectangle is inversely transformed, and convert this circumscribed rectangle into the first
An image processing method characterized in that the input division size corresponds to the buffer memory of.