JPH0442732U - - Google Patents
Info
- Publication number
- JPH0442732U JPH0442732U JP1990083644U JP8364490U JPH0442732U JP H0442732 U JPH0442732 U JP H0442732U JP 1990083644 U JP1990083644 U JP 1990083644U JP 8364490 U JP8364490 U JP 8364490U JP H0442732 U JPH0442732 U JP H0442732U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- case
- metal electrode
- adhesive applied
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/877—Bump connectors and die-attach connectors
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の実施例を示すＩＣパツケージ
の製造工程図、第２図はそのＩＣパツケージの裏
面斜視図、第３図はそのＩＣパツケージの基板へ
の実装状態の断面図、第４図はＳＯＰの斜視図、
第５図はＱＦＰの斜視図、第６図はＬＣＣの斜視
図、第７図はプラスチツク・フラツトの一部破断
斜視図である。
１１……ＩＣチツプ、１２……バンプ、１３…
…金属電極、１４……治具、１５……接着剤、１
６……ケース、１７……樹脂、２０……基板。
Fig. 1 is a manufacturing process diagram of an IC package showing an embodiment of the present invention, Fig. 2 is a rear perspective view of the IC package, Fig. 3 is a sectional view of the IC package mounted on a board, and Fig. 4 is a perspective view of SOP,
FIG. 5 is a perspective view of the QFP, FIG. 6 is a perspective view of the LCC, and FIG. 7 is a partially cutaway perspective view of the plastic flat. 11...IC chip, 12...bump, 13...
...Metal electrode, 14...Jig, 15...Adhesive, 1
6...Case, 17...Resin, 20...Substrate.
Claims (1)
、 (c) 該接着剤により前記金属電極の上面がケー
ス端面と同じかもしくは高くなるように固定され
るケースと、 (d) 該ケースと前記ＩＣチツプとの間を充填す
る樹脂とを具備するＩＣパツケージの構造。[Claims for Utility Model Registration] (a) an IC chip on which a metal electrode is formed; (b) an adhesive applied to the back surface of the IC chip; and (c) an adhesive applied to the top surface of the metal electrode. A structure of an IC package comprising: a case fixed at the same level or higher than the end face of the case; and (d) resin filling a space between the case and the IC chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990083644U JPH0442732U (en) | 1990-08-09 | 1990-08-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990083644U JPH0442732U (en) | 1990-08-09 | 1990-08-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0442732U true JPH0442732U (en) | 1992-04-10 |
Family
ID=31631480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990083644U Pending JPH0442732U (en) | 1990-08-09 | 1990-08-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442732U (en) |
-
1990
- 1990-08-09 JP JP1990083644U patent/JPH0442732U/ja active Pending