JPH0442828B2 - - Google Patents
Info
- Publication number
- JPH0442828B2 JPH0442828B2 JP59192893A JP19289384A JPH0442828B2 JP H0442828 B2 JPH0442828 B2 JP H0442828B2 JP 59192893 A JP59192893 A JP 59192893A JP 19289384 A JP19289384 A JP 19289384A JP H0442828 B2 JPH0442828 B2 JP H0442828B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- epitaxial layer
- region
- diffusion region
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/65—Integrated injection logic
Landscapes
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は注入形論理半導体装置（以下I2Lと称
す）に関し、逆形NPNトランジスタの電流増幅
率が小さくても、安定に動作する複合素子を構成
することができるI2Lに関するものである。[Detailed Description of the Invention] Industrial Application Field The present invention relates to an injection logic semiconductor device (hereinafter referred to as I 2 L), and provides a composite element that operates stably even if the current amplification factor of an inverted NPN transistor is small. It concerns I 2 L that can be configured.
従来例の構成とその問題点
従来この種のI2Lは第１図の断面図に示すよう
に構成されている。Ｐ型基板１の上にＮ型の埋め
込み層２を形成し、このＮ型埋め込み層の上にＮ
型エピタキシヤル層３を形成し、このＮ型エピタ
キシヤル層内にラテラルPNPトランジシタのコ
レクタ（これは逆形NPNトランジスタのベース
と共通）となる浅いＰ型拡散領域４と同トランジ
スタのエミツタとなる浅いＰ型拡散領域５とを形
成し、このNPTトランジスタのベース拡散領域
４内に浅いＮ型拡散領域６を形成して、逆形
NPNトランジスタを構成している。そして、前
記Ｎ型エピタキシヤル層は通常接地電位にバイア
スされている。Conventional Structure and its Problems Conventionally, this type of I 2 L has a structure as shown in the sectional view of FIG. An N-type buried layer 2 is formed on a P-type substrate 1, and an N-type buried layer 2 is formed on this N-type buried layer.
A type epitaxial layer 3 is formed, and in this N type epitaxial layer, there is a shallow P type diffusion region 4 which will become the collector of the lateral PNP transistor (this is common to the base of the inverted NPN transistor) and a shallow P type diffusion region 4 which will become the emitter of the lateral PNP transistor. A shallow N-type diffusion region 6 is formed within the base diffusion region 4 of this NPT transistor to form a reverse shape.
It constitutes an NPN transistor. The N-type epitaxial layer is normally biased to ground potential.
以上のように構成された従来のI2Lについてそ
の等価回路を第２図に示す。第２図中の符号（数
字）は第１図と各構成要素の符号と対応すると共
にＡ，ＢがPNPトランジスタで、Ｃ，Ｄが逆形
NPNトランジスタである。ＡとＣあるいはＢと
Ｄで１つのI2Lのセルを構成している。 FIG. 2 shows an equivalent circuit of the conventional I 2 L configured as described above. The symbols (numbers) in Figure 2 correspond to those of each component in Figure 1, and A and B are PNP transistors, and C and D are inverted transistors.
It is an NPN transistor. A and C or B and D constitute one I 2 L cell.
しかしながら、上記のような構成においては、
例えば、NPTトランジスタＣがONしている時、
同トランジスタＣのコレクタはPNPトランジス
タＢのコレクタ電流を引き込み、同PNPトラン
ジスタＢは活性領域にあるのに対し、NPNトラ
ンジスタＣを駆動するベース電流は、PNPトラ
ンジスタＡから供給される。この時、PNPトラ
ンジスタＡは飽和領域にあり、Ａのコレクタ電流
は、小さい値となつている。別の見方をすれば、
PNPトランジスタのVBE(P)は逆形トランジスタ
NPNトランジスタVBE(N)とPNPトランジスタの
VCE(Sat)の和より大きくなければならない。 However, in the above configuration,
For example, when NPT transistor C is ON,
The collector of transistor C draws the collector current of PNP transistor B, which is in the active region, while the base current driving NPN transistor C is supplied from PNP transistor A. At this time, the PNP transistor A is in the saturation region, and the collector current of A has a small value. If you look at it another way,
V BE(P) of a PNP transistor is an inverted transistor
NPN transistor V BE(N) and PNP transistor
Must be greater than the sum of V CE(Sat) .
すなわち、
VBE(P)＞VBE(N)＋VCE(Sat) ……(1)
で表わされる(1)式の成立する条件が必要である。
(1)式の左辺が右辺の差が大きい程、I2Lは安定に
動作するが、一方、I2Lの高速性を追及するため、
NPNトランジスタのベース領域（PNPトランジ
スタのコレクタ領域）に到達するホール（正孔）
の数を多くすると上記(1)式の左辺と右辺との左が
だんだん小さくなり、I2Lと動作として不安定に
なるという問題点を有していた。 That is, a condition is required for formula (1) expressed as V BE(P) > V BE(N) + V CE(Sat) (1) to hold.
The greater the difference between the left side and the right side of equation (1), the more stable I 2 L will operate, but on the other hand, in order to pursue high speed I 2 L,
Holes reaching the base region of the NPN transistor (collector region of the PNP transistor)
When the number of is increased, the left side of the above equation (1) gradually becomes smaller, and there is a problem that the operation becomes unstable due to I 2 L.
発明の目的
本発明は、注入形論理半導体装置で、逆形
NPNトランジスタの電流増幅率が小さくても１
以上あれば、安定に動作する素子構造を提供する
ことである。OBJECT OF THE INVENTION The present invention is an injection type logic semiconductor device.
Even if the current amplification factor of the NPN transistor is small, it is 1
The above provides an element structure that operates stably.
発明の構成
本発明の注入形論理半導体装置は、Ｐ型基板１
上にＮ型埋め込み層２を形成し、前記Ｎ型埋め込
み層２上に選択的にＰ型埋め込み領域９を形成
し、前記Ｎ型埋め込み層２および前記Ｐ型埋め込
み領域９のそれぞれの上にＮ型エピタキシヤル層
を形成し、直下に前記Ｐ型埋め込み領域９を有す
る前記Ｎ型エピタキシヤル層部を第１のＮ型エピ
タキシヤル層３−１、前記Ｐ型埋め込み領域９の
ない前記Ｎ型埋め込み層３上の前記Ｎ型エピタキ
シシヤル層部を第２のＮ型エピタキシヤル層３−
２と成し、前記第１のＮ型エピタキヤル層３−１
と前記第２のＮ型エピタキシヤル層３−２との間
を絶縁物質分離領域１０で分離し、前記第２のＮ
型エピタキシヤル層３−２内の主面から第１のＰ
型拡散領域４−１を浅く形成し、前記第１のＰ型
拡散領域４−１内に浅いＮ型拡散領域６を形成
し、前記第１のＮ型エピタキシヤル層３−１の主
面か前記Ｐ型埋め込み領域９まで達する深いＰ型
拡散領域１１を形成し、前記第１のＮ型エピタキ
シヤル層３−１内に前記第２、第３のＰ型拡散領
域４−２，５を浅く形成し、前記絶縁物質分離１
０領域を挟んで形成された前記第１のＰ型拡散領
域４−１と前記第２のＰ型拡散領域４−２とを接
続し、前記深いＰ型拡散領域１１と前記第１のＮ
型エピタキシヤル層３−１とを接続したことを特
徴とする構成にしたものであり、これにより逆形
PNPトランジスタの電流増幅率が小さくても安
定に動作するI2Lの構造を可能とするものである。Structure of the Invention The injection type logic semiconductor device of the present invention includes a P-type substrate 1
An N-type buried layer 2 is formed thereon, a P-type buried region 9 is selectively formed on the N-type buried layer 2, and an N-type buried layer 2 is formed on each of the N-type buried layer 2 and the P-type buried region 9. A type epitaxial layer is formed, and the N-type epitaxial layer portion having the P-type buried region 9 immediately below is formed into a first N-type epitaxial layer 3-1, and the N-type buried region without the P-type buried region 9 is formed. The N-type epitaxial layer portion on layer 3 is formed into a second N-type epitaxial layer 3-.
2, the first N-type epitaxial layer 3-1
and the second N-type epitaxial layer 3-2 are separated by an insulating material isolation region 10;
The first P from the main surface in the type epitaxial layer 3-2
A shallow type diffusion region 4-1 is formed, a shallow N type diffusion region 6 is formed in the first P type diffusion region 4-1, and a shallow N type diffusion region 6 is formed in the main surface of the first N type epitaxial layer 3-1. A deep P-type diffusion region 11 reaching the P-type buried region 9 is formed, and the second and third P-type diffusion regions 4-2 and 5 are shallowly formed in the first N-type epitaxial layer 3-1. forming the insulating material separation 1
The first P type diffusion region 4-1 and the second P type diffusion region 4-2 formed with the 0 region in between are connected, and the deep P type diffusion region 11 and the first N
The structure is characterized in that the epitaxial layer 3-1 is connected to the epitaxial layer 3-1.
This enables an I 2 L structure that operates stably even if the current amplification factor of the PNP transistor is small.
実施例の説明
以下本発明の一実施例について図面を参照しな
がら説明する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
第３図は本発明の一実施例におけるI2Lの要部
平面図を示すものであり、第４図および第５図は
同実施例における−′、および−′の各局
部断面図である。なお第１図と同一のものには同
一の符号をつけて説明を省略すいる。またＮ型埋
め込み層２は通常接地電位にバイアスされてい
る。 FIG. 3 shows a plan view of the main part of I 2 L in one embodiment of the present invention, and FIGS. 4 and 5 are local sectional views of -' and -' in the same embodiment. . Components that are the same as those in FIG. 1 are given the same reference numerals and their explanation will be omitted. Further, the N-type buried layer 2 is normally biased to a ground potential.
Ｐ型拡散領域９および深いＰ型拡散領域１１
は、共にラテラルPNPトランジスタのベースと
接地間に挿入させるダイオードのアノードを形成
している。これらは、コンタクト窓１２上の導電
性物質により、PNPトランジスタのベース領域
となるＮ型エピタキシヤル層３−２と接続され
る。さらに１０は酸化膜分離領域であり、これに
よりPNPトランジスタのコレクタ４（これは逆
形NPNトランジスタのベース）を２つに分割し
ており、これら２つの分割された浅いＰ型拡散領
域４−１と４−２とは導電性物質８で接続され
る。以上のように構成された本実施例のI2L構造
についてその等価回路を第６図に示す。例えば
NPNトランジスタＣがONしている時、PNPト
ランジスタＡはベースと接地間に挿入されたダイ
オードＥにより飽和領域に入ることはない。すな
わち、PNPトランジスタを飽和させずにI2Lを動
作させることができ、逆形NPNトランジスタの
電流増幅率が小さくも安定な動作が得られる。 P-type diffusion region 9 and deep P-type diffusion region 11
together form the anode of a diode inserted between the base of the lateral PNP transistor and ground. These are connected to the N-type epitaxial layer 3-2, which becomes the base region of the PNP transistor, by a conductive material on the contact window 12. Furthermore, 10 is an oxide film isolation region, which divides the collector 4 of the PNP transistor (this is the base of the inverted NPN transistor) into two, and these two divided shallow P-type diffusion regions 4-1 and 4-2 are connected by a conductive substance 8. FIG. 6 shows an equivalent circuit of the I 2 L structure of this embodiment constructed as described above. for example
When the NPN transistor C is ON, the PNP transistor A does not enter the saturation region due to the diode E inserted between the base and ground. That is, I 2 L can be operated without saturating the PNP transistor, and stable operation can be obtained even though the current amplification factor of the inverted NPN transistor is small.
発明の効果
以上の説明からも明らかなように、本発明は
I2LのPNPトランジスタのベースと接地間にダイ
オードを挿入することにより、高速性と安定動作
性能を兼ね備えた半導体素子であり、逆形NPN
トランジスタの電流増幅率が小さくてもよいこと
からこのNPNトランジスタのエミツタ・コレク
タ間の耐圧を高くすることができ集積回路におけ
る歩留りが大きく向上するという優れた効果がえ
られる。Effects of the Invention As is clear from the above explanation, the present invention has
By inserting a diode between the base and ground of the I2L PNP transistor, it is a semiconductor device that combines high speed and stable operation performance, and is an inverted NPN transistor.
Since the current amplification factor of the transistor may be small, the withstand voltage between the emitter and collector of this NPN transistor can be increased, which has the excellent effect of greatly improving the yield of integrated circuits.
第１図は従来例のI2Lの要部断面図、第２図は
同第１図示I2Lの等価回路図、第３図は本発明の
実施例I2Lの要部平面図、第４図は同実施例の局
部断面図、第５図は同実施例の局部断面図、第６
図は本発明のI2Lの等価回路図である。
１……Ｐ型基板、２……Ｎ型埋め込み層、３…
…Ｎ型エピタキシヤル層、４，５……浅いＰ型拡
散領域、６……浅いＮ型拡散領域、７……絶縁
膜、８……導電性物質、９……Ｐ型埋め込み領
域、１０……絶縁物質分離領域、１１……深いＰ
型拡散領域。
FIG. 1 is a sectional view of the main part of I 2 L of the conventional example, FIG. 2 is an equivalent circuit diagram of I 2 L shown in the first diagram, and FIG. 3 is a plan view of the main part of I 2 L of the embodiment of the present invention. Fig. 4 is a local sectional view of the same embodiment, Fig. 5 is a local sectional view of the same embodiment, and Fig. 6 is a local sectional view of the same embodiment.
The figure is an equivalent circuit diagram of I 2 L of the present invention. 1...P-type substrate, 2...N-type buried layer, 3...
...N type epitaxial layer, 4, 5... Shallow P type diffusion region, 6... Shallow N type diffusion region, 7... Insulating film, 8... Conductive material, 9... P type buried region, 10... ...Insulating material isolation region, 11...deep P
type diffusion region.
Claims (1)
Ｎ型埋め込み層上に選択的にＰ型埋め込み領域を
形成し、前記Ｎ型埋め込み層および前記Ｐ型埋め
込み領域のそれぞれの上にＮ型エピタキシヤル層
を形成し、直下に前記Ｐ型埋め込み領域を有する
前記Ｎ型エピタキシヤル層部を第１のＮ型エピタ
キシシヤル層、前記Ｐ型埋め込み領域のない前記
Ｎ型埋め込み層上の前記Ｎ型エピタキヤル層部を
第２のＮ型エピタキシヤル層と成し、前記第１の
Ｎ型エピタキシヤル層と前記第２のＮ型エピタキ
シヤル層との間を絶縁物質分離領域で分離し、前
記第２のＮ型エピタキシヤル層内の主面から第１
のＰ型拡散領域を浅く形成し、前記第１のＰ型拡
散領域内に浅いＮ型拡散領域を形成し、前記第１
のＮ型エピタキシヤル層の主面から前記Ｐ型埋め
込み領域まで達する深いＰ型拡散領域を形成し、
前記第１のＮ型エピタキシヤル層内に前記第２，
第３のＰ型拡散領域を浅く形成し、前記絶縁物質
分離領域を挟んで形成された前記第１のＰ型拡散
領域と前記第２のＰ型拡散領域とを接続し、前記
深いＰ型拡散領域と前記第１のＮ型エピタキシヤ
ル層とを接続したことを特徴とする注入形論理半
導体装置。1 An N-type buried layer is formed on a P-type substrate, a P-type buried region is selectively formed on the N-type buried layer, and an N-type buried layer is formed on each of the N-type buried layer and the P-type buried region. An epitaxial layer is formed, and the N-type epitaxial layer portion having the P-type buried region directly below is formed as a first N-type epitaxial layer, and the N-type epitaxial layer portion on the N-type buried layer without the P-type buried region is formed as a first N-type epitaxial layer. the epitaxial layer portion is a second N-type epitaxial layer, the first N-type epitaxial layer and the second N-type epitaxial layer are separated by an insulating material isolation region; The first layer from the main surface in the N-type epitaxial layer of
forming a shallow P-type diffusion region in the first P-type diffusion region; forming a shallow N-type diffusion region in the first P-type diffusion region;
forming a deep P-type diffusion region reaching from the main surface of the N-type epitaxial layer to the P-type buried region;
within the first N-type epitaxial layer;
A third P-type diffusion region is formed shallowly, the first P-type diffusion region and the second P-type diffusion region formed across the insulating material separation region are connected, and the deep P-type diffusion region is connected to the third P-type diffusion region. An injection type logic semiconductor device, characterized in that the region and the first N-type epitaxial layer are connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59192893A JPS6170747A (en) | 1984-09-14 | 1984-09-14 | Injection type logic semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59192893A JPS6170747A (en) | 1984-09-14 | 1984-09-14 | Injection type logic semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6170747A JPS6170747A (en) | 1986-04-11 |
| JPH0442828B2 true JPH0442828B2 (en) | 1992-07-14 |
Family
ID=16298726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59192893A Granted JPS6170747A (en) | 1984-09-14 | 1984-09-14 | Injection type logic semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6170747A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9260317B2 (en) | 2012-07-10 | 2016-02-16 | Nippon Sheet Glass Company, Limited | Method for producing granular material containing metal oxide |
-
1984
- 1984-09-14 JP JP59192893A patent/JPS6170747A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9260317B2 (en) | 2012-07-10 | 2016-02-16 | Nippon Sheet Glass Company, Limited | Method for producing granular material containing metal oxide |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6170747A (en) | 1986-04-11 |
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