JPH0442848B2 - - Google Patents

Description

[Detailed description of the invention] [Field of application of the invention]

The present invention relates to a drive circuit for a capacitive load such as a piezoelectric element, and more particularly to a drive circuit for a capacitive load that can be protected from abnormal currents such as when the capacitive load is short-circuited.

[Background of the invention]

Drive circuits for capacitive loads, such as piezoelectric elements, require high-speed, high-voltage pulse voltages.
A pulse voltage generating circuit as shown in Japanese Patent No. 27427 is known. FIG. 1 is a block diagram of the circuit, which includes first and second current source circuits connected in series between a first potential terminal 6 and a second potential terminal 7.
A switch is provided, and the switch is connected to the input terminal 4.
It is controlled to operate alternately by signals φ and from. For example, when a signal φ is input from the terminal 4, the switch 1 becomes conductive and supplies a constant current to the capacitive load connected to the output terminal 5. As the capacitive load 8 is charged with a constant current, the potential at the output terminal 5 rises with a constant slope (rate of rise = dv = dt), and the voltage value applied to the first potential terminal 6 increases. It fades and stops. At this time, the signal φ is applied to the switch 2, and the switch 2 is in a non-conductive state. Next, when a signal is input to the terminal 4, the switch 1 becomes non-conductive, the switch 2 becomes conductive, and the charge stored in the capacitive load 8 is discharged with a constant current. The potential of the output terminal 5 becomes the potential of the voltage terminal 7. Figure 2 shows the input and output waveforms at this time.
1 is an input signal, 2 is a voltage at the output terminal 5, 3 is a charging/discharging current flowing to the capacitive load 8, 15 is a charging current, and 16 is a discharging current, each flowing in the opposite direction. t is the rise time of the output voltage,
If the capacitance value of the load 8 is C, the output voltage is V, and the current is I, it is expressed by the following equation. Further, the fall time is also expressed by a similar formula. t=C×V/I...(1) From this equation, t can be shortened by increasing the current value. That is, a pulse voltage that rises or falls at high speed can be obtained. t is also the conduction time of the charging current (or discharging current in the case of fall time),
This will be referred to as normal operation time. Now, the first potential terminal 6 is set to a high level, the second potential terminal 7 is set to a low level, the first switch 1 is in a conductive state, and when the capacitive load 8 is to be charged, the output terminal 5 is set to a low level. In case of short circuit,
There is a problem in that an overcurrent flows through the path of the first potential terminal 6, the switch 1, and the output terminal 5, and the first switch is thermally destroyed. Next, if a short circuit occurs between the output terminal 5 and the high level side when the second switch 2 is turned on to discharge the charged capacitive load 8, the overcurrent will be transferred to the output terminal 5. , the switch 2, and the potential terminal 7, causing thermal damage to the switch 2. The overcurrent referred to here means that the first and second switches are switch elements that include current source circuits, so there is little variation in the current amplitude (current level value), but the energization time is longer than the normal operating time mentioned above. It is what it is.
Therefore, the switch element is unlikely to be destroyed instantly, but will be thermally destroyed after a period of time commensurate with its heat capacity. In the above circuit, the voltage relationship between the terminal potentials is reversed,
That is, the same problem occurs even if the potential terminal 6 is at a low level and the potential terminal 7 is at a high level. In order to detect overcurrent during such short circuits, a method has been considered in which a resistor is installed in the overcurrent path and the amplitude value (voltage level) is detected. I couldn't tell the difference.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitive load drive circuit that accurately detects and controls overcurrent when an output short circuit occurs, thereby preventing damage to the switch.

[Summary of the invention]

The capacitive load drive circuit according to the present invention that achieves the above object is characterized by a first potential terminal, a second potential terminal connected to a lower voltage potential than the first potential terminal, The first and second switch elements are connected in series between the first potential terminal and the second potential terminal, and the first and second switch elements are alternately in a conductive state and a non-conductive state. an input terminal for inputting a control signal to control the first and second
an output terminal drawn out from the connection point between the switch elements and connected to the capacitive load;
is interposed between one of the potential terminals of and the output terminal,
Current detecting means determines an overcurrent when the current flowing through the first and second switch elements becomes longer than during normal operation, and a signal from the current detecting means controls the first and second switch elements. The invention also includes a control means for controlling the conductive side of the element to an abnormally normal state.

[Embodiments of the invention]

The present invention will be explained in detail below based on the drawings. FIG. 3 shows a first embodiment of the present invention. In this figure, parts with the same reference numerals as those shown in FIG. 1 indicate specific examples of circuits that are the same or equivalent, respectively. Further, the current detection means 10 and the control means 1
The parts excluding 1 and 1 are from the above-mentioned JP-A-58-
This is the same as the conventional circuit known from Publication No. 27427. As shown in Fig. 3, the first switch 1, the second
The switch 2 and the inverter 3 are composed of transistors 45 to 50 and resistors. Among them, transistors 45 and 49 constitute a constant current switch operated by the input of signals φ and φ, respectively, and transistor 46 on the output terminal 5 side
By drawing out or cutting off the base currents of transistors 46, 47, and 50, transistors 46, 47, and 50 are turned on or off. In the circuit of this embodiment, the current detection means 10 is provided between the first potential (for example, power supply) terminal 6 and the first switch 1, and the control means 11 is provided between the base and emitter of the transistor 46. In normal operation, the switch is equivalently in an open state. Now, in normal operation, a signal φ is applied to input terminal 4.
When (“1”) is input, the transistor 45 constituting the constant current switch becomes conductive, and the base current is extracted from the transistor 46.
6 becomes conductive. The collector current of the transistor 46 becomes the base current of the transistor 47, making the transistor 47 conductive and supplying a charging current to a capacitive load (not shown) connected to the output terminal 5. This charging current is supplied from the first potential terminal 6 through the current detection means 10, but since it is less than a predetermined value for detecting overcurrent and outputting a detection signal,
Control means 11 does not operate. That is, equivalently, the switch is in an open state. At this time, a signal (“0”) is input to the transistor 49 due to the function of an inverter, and the transistor 49 is in a non-conducting (open) state.
Therefore, transistor 50 is reverse biased and in a non-conducting (open) state, and the potential at output terminal 5 is approximately at the first potential level. In this way, by inputting the signal φ to the input terminal 4, the first switch 1
It can be seen that the switch 2 becomes conductive and the second switch 2 becomes open (non-conductive). Next, when a signal is input to the input terminal 4, the first switch 1 becomes open, contrary to the above.
The second switch 2 becomes conductive, and the transistor 50 discharges the charge stored in the capacitive load.
The potential of the output terminal 5 is lowered to the same level as the second potential (eg, ground potential) terminal 7. At this time, the first
Since switch 1 is in the open (non-conducting) state,
No current flows through the current detection means 10. Therefore, the control means 11 remains open. Therefore, even if the conventional circuit is provided with the current detection means 10 and the control means 11, it is possible to generate a high voltage pulse for driving the capacitive load provided at the output terminal 5 during normal operation. A capacitor 120 and a resistor 121 provided as the current detection means 10 are connected in series, and this is connected in parallel to a resistor 44 provided between the first potential terminal 6 and the first switch 1. There is. Further, one terminal of the capacitor 120 is connected to the anode terminal of the thyristor 41 constituting the control means 11, and the other terminal is connected to the N gate of the thyristor 41 via the diode 42. Note that the diode 42 may be omitted if there is no malfunction due to noise. FIG. 4 shows the waveforms of various parts of the embodiment of the present invention. FIG. 4 1 shows the input signal φ to the terminal 4, FIG. 4 2 shows the current flowing through the resistor 44, and FIG. The potential at the connection point a between the resistor 121 and the resistor 44,
4 shows the potential at the connection point b between the capacitor 120 and the resistor 121, and FIG. 4 shows the current waveform at the N gate of the thyristor 41. In this embodiment, the signal φ is now applied to the input terminal 4.
is input and the first switch is in a conductive state, during normal operation, a capacitive load (not shown) is driven by the input of the signal φ, and the current ic in the resistor 44 is expressed by equation (1). flow for a period of t, thereby causing the fourth
As shown in FIG. 3, the voltage at the connection point a drops. However, because this period is short and there is a delay element with a time constant consisting of the capacitor 120 and the resistor 121, the potential at the connection point b cannot follow rapidly, and the potential fluctuation (voltage drop) is small. . Therefore, the voltage at the N gate of thyristor 41 is the ignition voltage
V _F is not reached, and the thyristor 41 does not become conductive. Therefore, the first switch 1 operates normally and the output terminal 5 becomes a high voltage. Considering the case where an output short circuit occurs at time K, an overcurrent flows through the resistor 44 (the current level at this time is approximately the same level as during normal operation, and the energization time is longer), and as shown in FIG. A current as shown by the broken line attempts to flow while the signal φ is input to the input terminal 4. However, as shown in FIG. 4, the potential at the connection point a drops rapidly, and as shown in FIG. decreases exponentially. After time t ₀ , when the potential at this point reaches the voltage V _F that turns on the thyristor 41, current is drawn from the N gate as shown in FIG. 4, and the thyristor 41 becomes conductive.
Diode 40 is inserted to compensate for the forward drop of thyristor 41 and transistor 46. Due to the conduction state of the thyristor 41, the base and emitter of the transistor 46 are short-circuited.
The first switch 1 is in a non-conducting (open) state,
The overcurrent is immediately cut off. As the overcurrent ebbs and flows, the potential at connection point a rises and the potential at connection point b also rises, returning to a steady state and maintaining this state until signal φ is input again and overcurrent flows. . As described above, according to one embodiment of the present invention,
Since the overcurrent that occurs when the output of the circuit that drives the switch and charges the capacitive load is short-circuited can be reliably detected and the overcurrent can be cut off, damage to the switch element due to overcurrent can be prevented. According to the circuit configuration of this embodiment, the current detection means 10 operates at a time _t0 delayed from the time when the short circuit occurs. The delay time _t0 can be set by CR, and is set to be longer than the driving time t of the capacitive load, and shorter than the time when the switch will be thermally destroyed by flowing overcurrent for a long time. ing.
This means that even if the peak value of the total load current is larger than the output short-circuit current of one drive circuit when many switches are driven in parallel, as will be described later, the current during normal and short-circuit conditions is There are clearly distinguishable effects. According to the circuit configuration of this embodiment, the current detection means 10 is provided between the first potential terminal 6 and the first switch 1, but the present invention is not limited to this. It may be provided anywhere along the path from the first potential terminal 6 to the other terminal of the capacitive load (the terminal not connected to the output terminal 5). FIG. 5 shows a second embodiment of the invention. In this figure, parts with the same reference numerals as those shown in FIGS. 1 and 2 indicate the same or equivalent parts, respectively. Also,
Channels 150, 151, and 152 are circuit parts in FIG. 4 excluding the current detection means 10 and the control means 11, and each channel has a first potential (e.g. power supply potential) terminal 6 and a second potential (e.g. (ground potential) is provided in parallel between the terminals 7. The current detection means 10 is connected to the first switch 1 of each channel as shown in the figure. Furthermore, the anode of the thyristor 41 constituting the control means 11 is newly provided with diodes 153, 154,
155 to the line 90 of each channel. The bias voltage V _B for the inverter is the fifth
As shown in the figure, the voltage is supplied to each channel from a potential terminal 160. During normal operation, each channel can be driven individually by a signal φ input to the input terminal 4 of each channel, and high voltage pulses can be generated at the output terminal 5 at different timings. Now, when each channel is driven by the signal φ at the same timing, the total load current of each channel flows through the resistor 44. The peak value of this total current is larger than the peak value of the overcurrent that flows when one channel is short-circuited. However, since the current flows only during the time period t shown in FIG. 2, the voltage detected by the current detection means 10 equipped with a delay element does not reach the voltage V _F that drives the thyristor. Next, when the output of each channel is at a high potential, if an output short circuit occurs only in channel 150, the short circuit current (overcurrent) tends to flow while the signal φ is input. At this time, the load currents of other channels have already become zero. The current detection means 10 detects the short circuit current at the time t ₀ shown in FIG. 3 and makes the thyristor 41 conductive. This allows the transistor 46 of each channel to
The base and emitter of the channel are short-circuited, and the first switches 1 of each channel are all opened, and the overcurrent is immediately cut off. Diodes 153, 154, and 155 prevent current from flowing backwards from one channel when line 90 of one channel is high and the other is low when each channel is operating individually. are doing. As described above, it can be seen that the above-described present embodiment can also prevent overcurrent at the time of short circuit. According to this embodiment, one set of current detection means 10
A large number of channels can be protected by the control means 11 and the control means 11, and when the circuit is integrated, it has an economically advantageous effect by increasing the integration density. In the embodiment described above, an overcurrent occurs in a capacitive load drive circuit used in a potential relationship in which the first potential terminal 6 is at a high level, and the second potential terminal 7 and the other terminal of the capacitive load are at a low level. Although protection has been described, the present invention is not limited thereto. For example, it can be applied to overcurrent protection in a capacitive load drive circuit used in a potential relationship in which the first potential terminal 6 and the other terminal of the capacitive load are at a high level, and the second potential terminal 7 is at a low level. In this case, if a short circuit occurs in the capacitive load when discharging the charge in the capacitive load, an overcurrent flows from the other terminal of the capacitive load toward the second potential terminal 7. Therefore, the current detection means may be provided in the path from the output terminal to the second potential terminal 7, and the control means may be provided between the second switch 2 and the second potential terminal 7.

【Effect of the invention】

As described above, according to the present invention, it is possible to obtain a capacitive load drive circuit that prevents overcurrent and does not destroy the switch even in the event of an output short circuit.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a pulse voltage generation circuit used in a conventional capacitive load driving circuit, Fig. 2 is a diagram for explaining the operation of Fig. 1, and Fig. 3 is a diagram for driving a capacitive load according to the present invention. A circuit diagram showing an example of the circuit,
FIG. 4 is a diagram showing the operating waveforms of FIG. 3, and FIG. 5 is a diagram showing a second embodiment of the present invention. 1...First switch, 2...Second switch, 3
...Inverter, 4...Input terminal, 5...Output terminal, 6
...first potential terminal, 7...second potential terminal, 8...capacitive load, 10...capacitive load, 11...control means,
12, 13...railway.

Claims (1)

[Claims] 1. A first potential terminal, a second potential terminal connected to a lower voltage potential than the first potential terminal, and a first potential terminal and a second potential terminal connected in series. an input terminal for inputting a control signal that alternately controls the first and second switch elements to be in a conducting state and a non-conducting state; an output terminal drawn out from the connection point between the two switch elements and connected to the capacitive load; and an output terminal interposed between one of the first and second potential terminals and the output terminal, A current detection means that determines an overcurrent when the current flowing through the element is longer than during normal operation; and a signal from the current detection means to detect the conducting side of the first and second switch elements. A drive circuit for a capacitive load, comprising: control means for controlling the voltage to an abnormally normal state. 2. In claim 1, the current detection means includes a first resistance element connected between a first potential end point and a first switch element, and a first resistance element connected in series.
A capacitor connected in parallel to the resistive element of
1. A drive circuit for a capacitive load, characterized in that the circuit comprises a resistor element, and uses a potential at a connection point between the capacitor and the second resistor element as a detection signal. 3 In claim 1 or 2,
A drive circuit for a capacitive load, characterized in that the capacitive load is an inkjet printer.