JPH0442919A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a shallow and narrow impurity layer in a highly integrated semiconductor device by heat-treating a silicon substrate at a high temperature in an unoxidizing atmosphere just before impurity ions are implanted and diffusing silicon atoms between excess lattices left in the silicon substrate. CONSTITUTION:A thin base thermal oxidation film a102 is formed on a p-type silicon substrate 101, a nitride film 103 is laminated, and the nitride film 103 and the thin oxidation film a102 in an element isolation region are selectively etched with a photoresist mask 104. The photoresist 104 is removed and a thermal oxidation film b105 is formed only on the surface of the silicon substrate 101 in the element isolation region by oxidation in a wet oxidizing atmosphere. The silicon substrate is heat-treated in an unoxidizing atmosphere to remove a silicon atom region 107 between excess lattices. The nitride film 103 and the oxidation film a102 are removed and then boron ion beams 109 are implanted only into the element isolation region with photoresist 108 used as a mask to form a channel stop 110. The channel stop 110 is activated by heat treatment.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of forming a shallow and narrow impurity region in a silicon substrate, which is effective in manufacturing a semiconductor device that requires a high degree of integration. Regarding the formation method, conventional techniques include a method of forming a shallow impurity layer with little spread in a silicon substrate, and a combination of impurity ion implantation and subsequent high-temperature heat treatment, regardless of the process before impurity ion implantation. This conventional technique will be explained using FIGS. 4(a) to (C). First, a p-type silicon substrate 401 is heat-treated in an oxidizing atmosphere to heat the surface of the silicon substrate 401. At this time, the silicon substrate 401 and the thermal oxide film 40 are formed.
A large amount of interstitial silicon atoms are released into the silicon substrate 401 from the interface 403 between the two, and an excess interstitial silicon atomic region 404 is formed in the silicon substrate 401 (fourth interstitial silicon atomic region 404).
Figure (a)). Next! Using the photoresist 405 as a mask, an n-type or p-type impurity ion beam 406 is implanted into the silicon substrate 401 to form an impurity region 407 (FIG. 4(b)). Finally, the silicon substrate 401 is subjected to high-temperature heat treatment in a non-oxidizing atmosphere to form an activated impurity region 407 in the silicon substrate (see Fig. 4 (C).
)).

Problems to be Solved by the Invention When using the conventional impurity layer formation technology, the following problems may occur: If there is a step of heat-treating the 6ζ silicon substrate in an oxidizing atmosphere before impurity ion implantation, the silicon substrate When the surface is oxidized, a large amount of silicon atoms that could not react with oxygen atoms are released into the silicon substrate and become interstitial silicon atoms4. The shallow impurity layer formed by ion implantation spreads by accelerated diffusion during heat treatment after ion implantation.
(See figure (C)). If the impurity distribution in the channel stop region of the fine MO3 field effect transistor widens in this way, the threshold voltage of the fine MO8 field effect transistor increases as the channel width becomes narrower (see Figure 5). This widening of the impurity distribution in the drain region causes a short channel effect (see FIG. 6) that decreases as the channel length becomes shorter, which has an adverse effect on the device.

The present invention provides a means for solving the problems in accordance with the present invention.It is an object of the present invention to provide a method for manufacturing a semiconductor device that forms a shallow and less spread impurity layer in a highly integrated semiconductor device. Immediately before the impurity ion implantation step, the substrate is subjected to a high temperature heat treatment step in a non-oxidizing atmosphere to remove excess interstitial silicon atoms remaining in the silicon substrate before the impurity ion implantation step at the silicon substrate/oxide film interface. By absorbing into existing kinks, recombining with vacancies, or diffusing the excess interstitial silicon atoms themselves, the concentration of excess interstitial silicon atoms in the silicon substrate is reduced, and the implanted impurities are absorbed by subsequent heat treatment. This method prevents accelerated diffusion caused by excess interstitial silicon atoms during the process and forms a shallow impurity region with little spread. When the method of the present invention is used, the temperature and time of the high-temperature heat treatment before impurity ion implantation can be adjusted to reduce the diffusion rate in the silicon substrate. Although it is possible to control the depth and spread of the formed impurity region by changing the excess interstitial silicon atomic concentration, the heat treatment after impurity ion implantation is also possible by reducing the excess interstitial silicon concentration in the silicon substrate. Although it is possible to suppress both the density and size of stacking faults that occur in the following example, the present invention will be explained in more detail based on the drawings (Example 1) Example of the fil of the present invention will be explained with reference to FIGS. 1(a) to (e). The first embodiment is an example in which the present invention is applied to a fine device isolation method. Thin base thermal oxide film a102 with a thickness of 20 nm
After forming a nitride film 103 with a thickness of 160 r+m, the nitride film 103 and thin oxide film a 102 in the element isolation region are selectively etched using a photoresist mask 104 (FIG. 1(a)).

Next, after removing the photoresist 104, 1000
＼ A thermal oxide film b105 with a thickness of 400 nm is formed only on the surface of the silicon substrate 101 in the element isolation region by oxidation in a wet oxidation atmosphere.At this time, the silicon substrate 101
A large amount of interstitial silicon atoms are released into the silicon substrate 101 from the interface 106 between the thermal oxide film b105 and the thermal oxide film b105, and an excess interstitial silicon atomic region 107 is formed in the silicon substrate 101 (FIG. 1(b)).

Next, the silicon substrate was heated at 1100°C in a non-oxidizing atmosphere.
Excessive interstitial silicon IJ atomic region 1 after 30 minute heat treatment 17
07 is removed (FIG. 1(C)). After removing the nitride film 103 and the oxide film a 102, a boron ion beam 1 is applied using a photoresist 108 with a thickness of 11000 nm as a mask.
09 was implanted only into the element isolation region under the conditions of 180 kev and 1 x 10 "er" to form the channel strike tube 11.
0 (FIG. 1(d)). Finally 900℃ 3
0 minutes heat treated and injected channelst tube 110
(Fig. 1(e)).

In this way, the excess interstitial silicon atomic region is removed by performing high-temperature heat treatment in a non-oxidizing atmosphere before implanting boron ions for channel stop. The spread of the stop into the active region (see Figure 1(e)) can be suppressed (therefore, the MOSFET formed in the active region)
It is strongly possible to suppress the so-called narrow channel effect, in which the threshold voltage of the transistor increases as the channel width of the transistor becomes narrower. A second embodiment of the present invention is shown in FIG. The method of the second embodiment will be explained with reference to ~(d).
8 This is an example applied to a method for forming source/drain regions of a field effect transistor. First, a 12 nm thick oxide film 1 is formed on a silicon substrate 201.
A gate electrode is formed of 11a 202, a doped polysilicon 203 with a thickness of 250 nm, and an NSG film 204 with a thickness of 250 nm (FIG. 2(a)). Next, in order to improve the breakdown voltage between the doped polysilicon 203 and the silicon substrate 201, the doped polysilicon 203 and the silicon substrate 201 are oxidized in a dry atmosphere at 900° C. for 20 minutes to form a thermal oxide film b205. At this time, a large amount of interstitial silicon atoms are released into the silicon substrate 201 from the interface 206 between the silicon substrate 201 and the thermal oxide film b205, and an excess interstitial silicon atomic region 207 is formed in the silicon substrate 201 (Fig. 2). (b)).

Next & Next Excess interstitial silicon atomic region 207 is removed by heat treatment at 900° C. for 30 minutes in a non-oxidizing atmosphere (FIG. 2(C)). Next, arsenic or BP2 ion beam 208 is applied using doped polysilicon 203 as a mask (7
For arsenic, 80 kev, 6 x 10”c
m"" 40 kev for BF2, 4 x
10 ICIn-2 ion implantation (after 7 days, 900℃,
Heat treatment is performed for 30 minutes to form source/drain regions 209 (FIG. 2(d)).

In this way, excessive interstitial silicon atoms f;
By applying heat treatment in a non-oxidizing atmosphere such as N or V, the spread of the source/drain region formed by arsenic or boron is reduced (see Figure 2 (d)).
By this, MOSFET
) - It is possible to suppress this so-called short channel effect as the threshold voltage of the transistor decreases as the channel length of the transistor becomes shorter.

"Two fruit" eaves - Example - λj - Refer to FIGS. 3(a) to (d) for the third embodiment of the present invention (
7 and explain. Third Embodiment (Friend) This is an example in which the present invention is applied to a method for forming a silicon gate protective film for a fine MO3iO3 field effect transistor.
Oxide film a302 with a film thickness of 12 nm and a film thickness of 250 nm on 01
nm doped polysilicon 303 and film thickness 250 nm
A gate electrode is formed of NSGM 304 (FIG. 3(a)).

Next, doped polysilicon 303 and silicon substrate 30
In order to improve the breakdown voltage between 1 and 2, the doped polysilicon 303 and silicon substrate 201 are oxidized in a dry atmosphere at 900° C. for 10 minutes to form a thin thermal oxide film b305.
At this time, a large amount of interstitial silicon atoms are released into the silicon substrate 301 from the interface 306 between the silicon substrate 301 and the thermal oxide film b305, and an excessive interstitial silicon atomic region 307 is formed in the silicon substrate 301 (Fig. 3). (b
)). Next, in an ammonia atmosphere, 900℃, 30℃
After heat treatment for a minute, a thin nitride film 3 is formed on the surface of the thermal oxide film b305.
At the same time as forming 08, the excess interstitial silicon atomic region 307 is removed (FIG. 3(C)).

Next 1 Arsenic or BFl! Using the doped polysilicon 303 as a mask, the ion beam 309 is 80 kev for arsenic, 6 x 10 "crn-" B
In the case of Fe, a 40 key, 4×10"cr" ion implantation is performed, followed by heat treatment at 900.degree. C. for 30 minutes to form source/drain regions 310 (FIG. 3(d)).

In this way, after the protective oxidation of polysilicon, vacancies are generated in the silicon substrate by performing heat treatment in an ammonia atmosphere instead of a non-oxidizing atmosphere. Excess interstitial silicon atoms generated in the silicon atoms (reduced by recombination with vacancies) can suppress the expansion of the source/drain regions formed by arsenic or boron (see Figure 3 (d)). As a result, the threshold voltage of the MOSFET transistor decreases as the channel length of the transistor becomes shorter.It is possible to suppress the so-called short channel effect. The film thickness 311 can be made thinner than that of the oxide film, which has a high dielectric constant compared to the oxide film, making it suitable for fine MQS transistors. It is also possible to suppress the accelerated diffusion of impurities in the silicon substrate due to excess interstitial silicon atoms remaining in the silicon substrate.Therefore, it is possible to control the amount of spread of the channel stop in the element isolation region into the active region. This makes it possible to suppress the narrow channel effect on MO8 field effect transistors formed in the active region.It also makes it possible to control the spread of impurity distribution in the source and drain regions of MO8 field effect transistors. Therefore, it is possible to suppress the short channel effect of MO3 field effect transistors.

[Brief explanation of drawings]

FIG. 1 is a partial process cross-sectional view for explaining an embodiment of the method for forming an element isolation region according to the present invention.
The figure is a partial process cross-sectional view for explaining an embodiment of the method for forming the source/drain regions of a micro MO8 field effect transistor according to the present invention. Figure 4 is for explaining the conventional method for forming shallow and narrow impurity regions. Figure 5 is a characteristic diagram for explaining the narrow channel effect of the MO8 field effect transistor. Figure 6 is a characteristic diagram for explaining the short channel effect of the MO8 field effect transistor. 301...Silicon substrate 107.
207.307...excess interstitial silicon atomic region 11
0... Expansion of channel stop top, 210... Expansion of source/drain region. Name of agent: Patent attorney Shigetaka Awano (1 person) III Silicon Zengo J11! g Goko between Shisofunjima child Naruko Yanel stop channel stop spread silicon Kureitako Yakirstopte +1 Rusttsua's wide pi Rishilikov IL yoke 111 leopard% child darkness silicon! IP! 1st gloss υl- Figure 1 of the first report MO5I-Sensor/LJ of the transistor Figure r-Tos transistor length

Claims (4)

[Claims] (1) A step of growing an oxide film in an oxidizing atmosphere on the surface of a semiconductor substrate of one conductivity type, a step of heat-treating the semiconductor substrate at a high temperature in a non-oxidizing atmosphere following the step, and the step of the step. A method for manufacturing a semiconductor device, comprising the steps of later ion-implanting p-type or n-type impurities into the semiconductor substrate, and heat-treating the semiconductor substrate. (2) A method for manufacturing a semiconductor device according to claim 1, characterized in that a p-type or n-type source/drain is formed with an ion-implanted impurity concentration of 1×10^2^0 cm^-^3 or more. (3) The semiconductor device according to claim 1, wherein the step of growing the oxide film in an oxidizing atmosphere is a step of selectively forming a gate electrode on the semiconductor substrate and protectively oxidizing the gate electrode. manufacturing method. (4) A step of selectively forming a gate electrode on a semiconductor substrate of one conductivity type, a step of oxidizing the semiconductor substrate and the gate electrode, a step of performing a subsequent nitriding treatment, and a step of non-conductive treatment immediately after the step of oxidizing the semiconductor substrate and the gate electrode. A method for manufacturing a semiconductor device, comprising the steps of performing high-temperature heat treatment in an oxidizing atmosphere, ion-implanting p-type or n-type impurities after the step, and heat-treating the semiconductor substrate.